Results 71 to 80 of about 2,350 (180)

A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC

IEEE Open Journal of the Solid-State Circuits Society
This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and $4\times $ – $36\times $ lower sampling capacitor
Sumukh Prashant Bhanushali, Arindam Sanyal   +1 more
doaj   +1 more source

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

Energies, 2018
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be ...
Behnam Samadpoor Rikan, Sang-Yun Kim, Hamed Abbasizadeh, Arash Hejazi, Reza E. Rad, Khuram Shehzad, Keum Cheol Hwang, Youngoo Yang, Minjae Lee, Kang-Yoon Lee   +9 more
doaj   +1 more source

Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC. [PDF]

Micromachines (Basel), 2023
Wang YJ, Wang P, Wan LX, Jin Z.
europepmc   +1 more source

A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications. [PDF]

Micromachines (Basel), 2022
Hu Y, Tang B, Hu L, Liang H, Li B, Wu Z, Liu X.   +6 more
europepmc   +1 more source

A command-driven 16-bit SAR ADC

Dianzi Jishu Yingyong
This paper presents a command-driven 16-bit successive approximation register analog-to-digital converter (SAR ADC) designed to enable precise real-time monitoring of target devices. The ADC performs conversion only upon receiving commands from the host,
Qin Kefan, Zhang Yusheng, Zheng Xinyue, Ma Wei, Hu Weibo   +4 more
doaj   +1 more source

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

IEEE Access, 2019
This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution ...
Byungjoo Oh, Kyeonghwan Park, Jae Joon Kim   +2 more
doaj   +1 more source

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator. [PDF]

Sensors (Basel), 2022
Verma D, Shehzad K, Kim SJ, Pu YG, Yoo SS, Hwang KC, Yang Y, Lee KY.   +7 more
europepmc   +1 more source

8.4‐to‐16‐bit resolution, 1‐to‐16 kHz bandwidth ADC with programmable‐gain functionality for multi‐sensor applications

Electronics Letters, 2019
A resolution‐reconfigurable, bandwidth‐scalable analogue‐to‐digital converter (ADC) with programmable‐gain (PG) functionality for a multi‐sensor system, which encompasses various signals such as bio‐signals and battery‐level, is presented.
J. Rhee, S. Kim
doaj   +1 more source

A 12-b Subranging SAR ADC Using Detect-and-Skip Switching and Mismatch Calibration for Biopotential Sensing Applications. [PDF]

Sensors (Basel), 2022
Nguyen CL, Phan HN, Lee JW.
europepmc   +1 more source

A 10 MHz‐BW 85 dB‐SNDR 4th‐order sturdy MASH 2‐0 noise shaping SAR ADC with 2nd‐order gain‐error‐shaping technique

Electronics Letters
The multi‐stage noise shaping (MASH) ΣΔ ADC has a good potential to achieve high‐order noise shaping (NS) and high resolution. However, it suffers from quantization noise leakage caused by the mismatch between the analogue NS filter and the digital ...
Lizhen Zhang, Jianhui Wu
doaj   +1 more source