Results 201 to 210 of about 582,151 (290)

A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW

IEEE Journal of Solid-State Circuits, 2023
Compact, high-bandwidth analog-to-digital converters (ADCs) with moderate resolution are a critical building block in high-speed communication links. In this work, a hybrid time and voltage domain ADC is presented that uses a single high-speed voltage-to-
A. Whitcombe, Chun C. Lee, Asma Beevi Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, B. Carlton, Peter Sagazio, S. Pellerano, C. Hull   +9 more
semanticscholar   +1 more source

10.4 A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting

IEEE International Solid-State Circuits Conference, 2023
Recent years have witnessed the development of high-resolution ADCs >14b utilizing the power-efficient SAR topology at medium speed (1-20MSps) [1–4]. However, high-resolution discrete-time Nyquist ADCs are difficult to drive, especially at high sampling ...
Manxin Li, C. Lee, A. ElShater, Yuichi Miyahara, Kazuki Sobue, K. Tomioka, U. Moon   +6 more
semanticscholar   +1 more source

A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment

IEEE Journal of Solid-State Circuits, 2023
This article presents a power efficient and process, voltage, and temperature (PVT) robust pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that quantizes signals in both voltage and time domains.
Haoyi Zhao, F. Dai
semanticscholar   +1 more source

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

IEEE Transactions on Biomedical Circuits and Systems, 2022
This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is ...
Yuhua Liang, Changying Li, Shubin Liu, Zhangming Zhu   +3 more
semanticscholar   +1 more source

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

IEEE Journal of Solid-State Circuits, 2023
This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process.
Xiaofeng Guo, Run Chen, Zhenqi Chen, Bin Li   +3 more
semanticscholar   +1 more source

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier

IEEE Journal of Solid-State Circuits, 2023
This work presents a 14-bit 500 MS/s single-channel pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC) with an adaptively biased floating inverter amplifier (AB-FIA) as the residue amplifier (RA) and a hybrid reference ...
Wenning Jiang, Yan Zhu, Chixiao Chen, Hao Xu, Qi Liu, Meilin Liu, R. Martins, Chi-Hang Chan   +7 more
semanticscholar   +1 more source

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2023
This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter ...
Dengquan Li, Xin Zhao, Yi Shen, Shubin Liu, Zhangming Zhu   +4 more
semanticscholar   +1 more source

A 0.6-V 12-bit Set-and-Down SAR ADC With a DAC-Based Bypass Window Switching Method

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2023
This brief proposes a digital-to-analog-converter-based (DAC-based) bypass window switching method for the successive-approximation register analog-to-digital converter (SAR ADC). The proposed method defines the size of the bypass window by switching the
Wei-En Lee, Tsung-Hsien Lin
semanticscholar   +1 more source

A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator

IEEE Journal of Solid-State Circuits, 2023
This article presents a second-order noise shaping (NS) pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with fully passive NS and a second-order gain error shaping (GES) based on a Quantization-Prediction-Unrolled ...
Hongshuai Zhang, Yan Zhu, R. P. Martins, Chi-Hang Chan   +3 more
semanticscholar   +1 more source

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

IEEE Journal of Solid-State Circuits, 2022
This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration.
J. Lagos, N. Markulić, B. Hershberg, D. Dermit, M. Shrivas, E. Martens, J. Craninckx   +6 more
semanticscholar   +1 more source