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Transition Point Estimation Using RC-Filtered Square Wave for Calibration of SAR ADC
IEEE Transactions on Circuits and Systems - II - Express Briefs, 2023Successive-approximation register (SAR) ADCs are susceptible to non-linearities due to capacitor mismatch. This brief proposes a transition points-based calibration of the SAR ADC using an RC-filtered square wave by looking at the histogram of output ...
Sai Sanjeet, Shruti Konwar, B. Sahoo
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IEEE Transactions on Circuits and Systems II: Express Briefs, 2017
The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion ...
Chi-Hang Chan +5 more
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The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion ...
Chi-Hang Chan +5 more
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An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2023This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the ...
Yi Shen +6 more
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IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2023
This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to ...
Mingqiang Guo +5 more
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This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to ...
Mingqiang Guo +5 more
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IEEE Journal of Solid-State Circuits, 2023
A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the $\Delta $ - $\Sigma $ and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency.
Shulin Zhao +6 more
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A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the $\Delta $ - $\Sigma $ and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency.
Shulin Zhao +6 more
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Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011
In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs.
Albert H. Chang +2 more
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In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs.
Albert H. Chang +2 more
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IEEE International Solid-State Circuits Conference, 2023
Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution.
Mingtao Zhan, Lu Jie, Nan Sun
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Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution.
Mingtao Zhan, Lu Jie, Nan Sun
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IEEE Journal of Solid-State Circuits, 2021
To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed.
Tzu-Han Wang +4 more
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To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed.
Tzu-Han Wang +4 more
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Unified ADC nonlinearity error model for SAR ADC
Measurement, 2008Abstract The paper introduces a new ADC static nonlinearity model focusing on SAR ADC which is labelled the unified ADC nonlinearity error model. The model can also cover any other ADC architectures that have stochastic and/or periodic extremes in their integral nonlinearity function superposed on a “slowly changing” background. In the proposed model
Linus Michaeli +2 more
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IEEE Transactions on Circuits and Systems - II - Express Briefs, 2021
This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure.
Pinyun Yi +5 more
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This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure.
Pinyun Yi +5 more
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