Results 231 to 240 of about 19,913 (253)
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IEEE Transactions on Industrial Electronics, 2014
This paper presents a novel feedback (FB) controller design on the basis of a circle condition for the fast and precise positioning of mechatronic systems. In general FB controller design, both disturbance suppression and system stability (i.e., gain and phase margins) are essential indexes to provide the desired control performance. A circle condition-
Yoshihiro Maeda, Makoto Iwasaki
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This paper presents a novel feedback (FB) controller design on the basis of a circle condition for the fast and precise positioning of mechatronic systems. In general FB controller design, both disturbance suppression and system stability (i.e., gain and phase margins) are essential indexes to provide the desired control performance. A circle condition-
Yoshihiro Maeda, Makoto Iwasaki
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A low-noise fast-settling PLL frequency synthesizer for CDMA receivers
2004 International Symposium on System-on-Chip, 2004. Proceedings., 2005A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond
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A Low-Power Fast-Settling Bond-Wire Frequency Synthesizer With a Dynamic-Bandwidth Scheme
IEEE Transactions on Circuits and Systems I: Regular Papers, 2012This paper presents a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72–1.74 GHz for a 100 kb/s Gaussian frequency shift keying (GFSK) based transceiver suitable for wireless sensor network (WSN) applications. We propose several new techniques for lowering the power consumption in the frequency synthesizer.
Bo Zhao 0003 +2 more
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Correlation of frequency hopped VCO phase settling to varactor transient capacitance
Proceedings of the 1999 Joint Meeting of the European Frequency and Time Forum and the IEEE International Frequency Control Symposium (Cat. No.99CH36313), 2003Microwave VCO and system designers should be aware that attoFarad level changes in the dynamic performance of a varactor can correlate to changes in system settling response of fast hopping frequency synthesizers. It is theorized that a moisture/silicon interaction occurred within a packaged varactor diode due to imperfect wafer processing of the die ...
L.A. Mallette +4 more
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A low-noise CMOS frequency synthesizer with an ultra-short settling time
2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2016In this work, a novel self-injection-locked (SIL) loop is incorporated into a CMOS frequency synthesizer for fast frequency switching. The proposed SIL loop is based on an injection-locked oscillator (ILO) which behaves as an active delay unit to suppress the excess phase noise produced owing to the large phase-locked loop (PLL) bandwidth. Consequently,
Chieh-Hsun Hsiao +3 more
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Improving the settling time of a digital phase-lock frequency synthesizer
International Journal of Electronics, 1987The settling time of a digital phase-lock frequency synthesizer is improved by using a digital time to voltage converter (DTVC) to replace the loop filter. The synthesizer is then analysed as a sampled data control system. Analysis and experimental results show that an improvement in the settling time is obtained compared with the conventional phase ...
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A fast settling on-chip low-dropout regulator with a robust frequency compensation scheme
20th Iranian Conference on Electrical Engineering (ICEE2012), 2012An on-chip low-dropout (LDO) voltage regulator with a novel technique to improve the settling time and a robust frequency compensation scheme is presented in this paper. The total capacitance required for the utilized compensation topology is only 2.8 pF.
Mortaza Mojarad, Mohammad Yavari
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Fast settling ultra low phase noise synthesizer for frequency agile RADARS
2015 International Conference on Microwave, Optical and Communication Engineering (ICMOCE), 2015Synthesizer phase noise and settling time of RADAR transmitter impacts performance of the radar system. Ability to detect moving-target signals superimposed with clutter depends on spectral purity level of the transmitter signal i.e. phase noise combined with other spurii. Lower the phase noise, stronger the ability to detect moving-target signals. Low
T. Venkatmuni +3 more
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Low power consumption and fast settling frequency synthesizer for TDMA-TDD systems
IEEE 43rd Vehicular Technology Conference, 2002A novel configuration for a low power consumption, fast settling frequency synthesizer is presented. The synthesizer employs two sets of a sample-hold voltage-controlled oscillator (VCO) and a carrier switch which selects VCO output as the output of the synthesizer burst-by-burst.
K. Seki, M. Mizoguchi, S. Kato
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2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2003
The loop bandwidth of PLL frequency synthesizers involves design tradeoffs between the lock time and reference feedthrough. The adaptive PLL solves the problem by increasing the bandwidth in the acquiring stage for faster lock speed and reducing the bandwidth after the loop locks for lower spur level.
Yiwu Tang +2 more
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The loop bandwidth of PLL frequency synthesizers involves design tradeoffs between the lock time and reference feedthrough. The adaptive PLL solves the problem by increasing the bandwidth in the acquiring stage for faster lock speed and reducing the bandwidth after the loop locks for lower spur level.
Yiwu Tang +2 more
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