Results 211 to 220 of about 19,913 (253)

A Fast-Settling Frequency Synthesizer Using Statistical Frequency Measurement Method

IEEE Transactions on Instrumentation and Measurement, 2022
Yi-Jan Chen, Yun-Chih Lu, Yi Ting Lin
exaly   +2 more sources

A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement

IEEE Transactions on Circuits and Systems II: Express Briefs, 2018
This brief presents a frequency compensation technique to improve the settling time in driving moderate capacitive load (10–20 pF) of a low-power ( $ {\mu }{\mathrm{ W}}$ ) class-AB super buffer, wherein previously reported super buffers exhibit poor stability performance. From post-layout simulations in a 0.18- $ {\mu }\text{m}$ CMOS process,
Woradorn Wattanapanitch
exaly   +2 more sources

Low-Power Frequency-Locked Loop Circuit with Short Settling Time

2022 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022
A phase-locked loop (PLL) is an important and commonly used electronic circuit in various electronic systems. Its main drawback is the use of an RC low-pass filter which takes up the majority of the PLL area on the chip. The RC low-pass filter is necessary to ensure the PLL stability.
Andro Zamboki, Leo Gocan, Niko Bako, Josip Mikulic, Gregor Schatzberger, Adrijan Baric   +5 more
openaire   +1 more source

A fast-settling PLL frequency synthesizer with direct frequency presetting

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006
A PLL frequency synthesizer with frequency presetting is implemented in a 0.35mum CMOS process and occupies 0.4mm2. The output frequency is between 560 and 820MHz, the supply is 3.3V, the measured settling time is
Xiaofei Kuang, Nanjian Wu
openaire   +1 more source

A fast-settling GaAs-enhanced frequency synthesizer

IEEE Journal of Solid-State Circuits, 1992
An indirect, phase-locked-loop (PLL), GaAs-enhanced frequency synthesizer with 700 ns loop settling time has been developed. The two-chip GaAs insertion reduced the size of an existing synthesizer from 90 in/sup 3/ to only 30 in/sup 3/. The 6.0 in*5.5 in.*0.9 in module contains a 400 gate GaAs programmable divider and a sample and hold (S/H) which ...
John F. Naber, Hausila P. Singh, William J. Tanis, Andrew J. Koshar, Gregory L. Segalla   +4 more
openaire   +1 more source

GaAs prescalers and counters for fast-settling frequency synthesizers

IEEE Journal of Solid-State Circuits, 1990
A number of low-power GaAs direct-coupled FET logic (DCFL) components developed for use in compact, fast-settling phase-locked-loop-type frequency synthesizer applications are discussed. These components include a divide-by-two circuit (2.7 GHz, 1.3 mW), a dual-modulus (/10/11) prescaler (2.4 GHz, 15 mW), a 4-b ripple counter (2.4 GHz, 4.6 mW), a 4-b ...
Hausila P. Singh, Robert A. Sadler, William J. Tanis, Alan N. Schenberg   +3 more
openaire   +1 more source

Settling time minimization in PLL frequency synthesizers

ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605), 2003
To minimize the frequency settling time, an attempt to optimize the parameters of the 3/sup rd/ order PLL frequency synthesizer (FS) is described in this paper. Using the quasi-continuous analysis, the analytical expressions for calculating the suboptimal ratios of parameters for the loop filter are derived, expecting the linear transfer characteristic
M. Min, V. Mannama, T. Paavle
openaire   +1 more source

A fast-settling GaAs enhanced frequency synthesizer

[1991] GaAs IC Symposium Technical Digest, 2002
An indirect, phase-locked loop, GaAs enhanced frequency synthesizer with 700-ns settling time has been developed using a 0.4 mu m gate multifunction self-aligned gate (MSAG) process. The two-chip GaAs insertion reduces the size of an existing synthesizer from 90 cubic inches to only 30 cubic inches. The 6.0*5.5*0.9 inch module contains a 400-gate, GaAs
J.F. Naber, H.P. Singh, R.A. Sadler, W.J. Tanis, A. Koshar, G. Segalla   +5 more
openaire   +1 more source

A low power fast-settling frequency-presetting PLL frequency synthesizer

Journal of Semiconductors, 2010
This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18 μm CMOS process. A low power mixed-signal LC VCO, a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time ...
Geng Zhiqing, Yan Xiaozhou, Lou Wenfeng, Feng Peng, Wu Nanjian   +4 more
openaire   +1 more source

Method for measuring settling phenomena by means of frequency domain instrumentation

Review of Scientific Instruments, 2016
The paper deals with the analysis of settling phenomena that characterize the step response of digital to analog converters, amplifiers, and several other devices. Settling is described by means of a minimal second order model that is suitable to account for the distortion terms recognized in the signal spectrum.
M. D’Apuzzo, M. D’Arco, A. Liccardo, M. Vadursi   +3 more
openaire   +4 more sources