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Ultrathin Silicon-an-Insulator (SOI) Wafer for Compliant Substrate
2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), 2017Compliant substrate is one of the most promising approaches for heteroepitaxy of the semiconductor devices. SOI wafer is the only commercial structure used for the compliant substrate researches. Yet, previous studies reported ineffectiveness of SOI as a compliant substrate for thickness regions above 10 nm.
Shinyoung Noh +4 more
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Overview of fully depleted silicon-on-insulator (SOI) technology
Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488), 2004This paper examines the advantages and disadvantages of thin-film, fully depleted (FD) silicon-on-insulator (SOI) technology devices compared to bulk devices, describing their desirability and suitability for low-voltage and low-power very large-scale integrated (VLSI) circuits.
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T-Shaped Body Silicon-on-Insulator (SOI) MOSFET
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006A novel partially-depleted (PD) silicon-on-insulator (SOI) MOSFET with a T-shaped body (TSB) is proposed for the first time. Simulation results demonstrate that the proposed structure provides nano-scaled PD SOI devices with much better short channel effect immunity and sub-threshold characteristics than those of UTB SOI devices.
Ji Cao +5 more
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Laser Processing in Silicon on Insulator (SOI) Technologies
1984Silicon on insulator (SOI) technologies are an attractive alternative for VLSI circuit manufacturing, owing to such advantages as reduced parasitic capacitances, latch-up immunity and insensitivity to alpha particles. SOI technologies may be also viewed as a first but necessary step towards 3-D integration.
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Silicon-on-insulator (SOI) wafer fabrication for MEMS applications
SPIE Proceedings, 2003In this paper, it is shown that Silicon-On-Insulator (SOI) wafers with good surface finish and thickness control can be realized using Silicon Fusion Bonding along with an optimized ethylenediamine-pyrocatechol-water (EDP) etching approach. Single crystal diaphragms of 11 μm thickness have been fabricated using these SOI wafers.
Bhimanadhuni R. KotiReddy +3 more
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A seeded-channel silicon-on-insulator (SOI) MOS technology
IEEE Electron Device Letters, 1985An improved silicon-on-insulator (SOI) MOSFET transistor structure is presented. The structure retains the density and low-capacitance advantages of SOI, but places the transistor channel region in the single-crystal silicon substrate. This "seeded-channel" configuration avoids floating-body effects and ensures that defects in the SOI will not affect ...
W. Baerg +7 more
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Extreme-submicrometer silicon-on-insulator (SOI) MOSFETs.
1994Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. ; Includes bibliographical references (leaves 200-213). ; by Lisa T. Su. ; Ph.D.
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Process and Simulation design of Silicon-On-Insulator (SOI) NMOS
2023 IEEE Nanotechnology Materials and Devices Conference (NMDC), 2023Zih-Fei Chen +4 more
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SOI (Silicon-on-insulator)—materials and devices
Microelectronics Reliability, 1997openaire +1 more source