Results 191 to 200 of about 11,532 (237)
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Chocolat/SMV: A Translator from CafeOBJ into SMV
Sixth International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'05), 2005Chocolat/SMV is a translator that takes a CafeOBJ specification of a transition system called an OTS and generates an SMV specification of a finite version of the OTS. The primary purpose of the translation is to find errors lurked in CafeOBJ specifications of OTSs with SMV.
Kazuhiro Ogata 0001 +3 more
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Verify UML statecharts with SMV
Wuhan University Journal of Natural Sciences, 2001Formal verification has been widely needed in the development of safety critical systems. In order to introduce the design verification activity in UML developing process, we have developed a verifier of UML Statecharts by using the model checker SMV.
Chen Hai-yan +3 more
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SMV: Selective Multi-Versioning STM
2011We present Selective Multi-Versioning (SMV), a new STM that reduces the number of aborts, especially those of long read-only transactions. SMV keeps old object versions as long as they might be useful for some transaction to read. It is able to do so while still allowing reading transactions to be invisible by relying on automatic garbage collection to
Dmitri Perelman +3 more
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2021
Soybean (Glycine max) is a species of legume widely grown for its edible bean which has numerous uses. It got its origin in China from where it migrated to Korea and then to Europe and America. The present study highlights the variation of susceptibility of Soybean plants to mild and severe SMV strains when treated at various temperatures before and ...
Nirmala Koranga +1 more
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Soybean (Glycine max) is a species of legume widely grown for its edible bean which has numerous uses. It got its origin in China from where it migrated to Korea and then to Europe and America. The present study highlights the variation of susceptibility of Soybean plants to mild and severe SMV strains when treated at various temperatures before and ...
Nirmala Koranga +1 more
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Verifying a gigabit ethernet switch using SMV
Proceedings of the 41st annual Design Automation Conference, 2004We use model checking techniques to verify a switching block in a new Gigabit Ethernet switch - BCM5690. Due to its dynamic nature, this block has been traditionally difficult to verify. Formal techniques are far more efficient than simulation for this particular design. Among 26 design errors discovered, 22 are found using formal methods.
Yuan Lu, Mike Jorda
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Medarbejderaktieordninger i SMV
2022The purpose of this master’s thesis is to clarify opportunities and challenges regarding employee stock purchase plans in SMEs’. The theoretical view is amongst other things, based on the principal-agent. The theory is relevant for this master’s thesis because the stakeholders want their employees to make decisions in a greater extent of their interest
Jensen, Rasmus +1 more
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1993
In order to apply symbolic model checking to real problems, we need expressive languages that we can use to describe our model at a suitably high level (eg., a gate level schematic is probably not a high enough level). For our purposes, this means the language must provide operations on suitable high level types (such as symbolic enumerated types), and
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In order to apply symbolic model checking to real problems, we need expressive languages that we can use to describe our model at a suitably high level (eg., a gate level schematic is probably not a high enough level). For our purposes, this means the language must provide operations on suitable high level types (such as symbolic enumerated types), and
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Using SMV for cryptographic protocol analysis
ACM SIGOPS Operating Systems Review, 2001SMV is a tool for checking finite state systems. In this paper, a methodology is presented for using SMV to analyze cryptographic protocols. We illustrate the feasibility of the approach by analyzing Needham-Schroeder Public-Key Protocol and discover the well-known attack upon the protocol.
Yuqing Zhang +3 more
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Mapping SMV models to event-B models
2010 5th International Design and Test Workshop, 2010This paper presents an approach which integrates two formal verification techniques, model checking and the Event-B method in a way that makes it possible to benefit from the advantages of both methods in the design flow. This integration allows the user to write his model and verifies it using model checking techniques/tools.
Samah Hassan +2 more
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