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Optimal Stack Layout in a Sea Container Terminal with Automated Lifting Vehicles [PDF]
International Journal of Production Research, 2014 Container terminal performance is largely determined by its design decisions, which include the number and type of quay cranes, stack cranes, transport vehicles, vehicle travel path and stack layout. We investigate the orientation of the stack layout (parallel or perpendicular to the quayside) on the throughput time performance of the terminals ...
Debjit Roy +3 more
semanticscholar +11 more sources
Stacks, Queues and Tracks: Layouts of Graph Subdivisions [PDF]
Discrete Mathematics & Theoretical Computer Science, 2005 A k-stack layout (respectively, k-queuelayout) of a graph consists of a total order of the vertices, and a partition of the edges into k sets of non-crossing (non-nested) edges with respect to the vertex ordering.
Vida Dujmović, David R. Wood
doaj +8 more sources
Stack and Queue Layouts via Layered Separators [PDF]
Journal of Graph Algorithms and Applications, 2017 It is known that every proper minor-closed class of graphs has bounded stack-number (a.k.a. book thickness and page number). While this includes notable graph families such as planar graphs and graphs of bounded genus, many other graph families are not closed under taking minors.
Vida Dujmović, Fabrizio Frati
core +7 more sources
The Parameterized Complexity of Extending Stack Layouts [PDF]
International Symposium Graph Drawing and Network VisualizationAn $\ell$-page stack layout (also known as an $\ell$-page book embedding) of a graph is a linear order of the vertex set together with a partition of the edge set into $\ell$ stacks (or pages), such that the endpoints of no two edges on the same stack alternate.
Thomas Depian +3 more
semanticscholar +6 more sources
Stack Layout Randomization with Minimal Rewriting of Android Binaries
International Conference on Information Security and Cryptology, 2016 Stack-based attacks typically require that attackers have a good understanding of the stack layout of the victim program. In this paper, we leverage specific features on ARM architecture and propose a practical technique that introduces randomness to the stack layout when an Android application executes.
Liang Yu +7 more
semanticscholar +6 more sources
Stacked Dependency Networks for Layout Document Structuring [PDF]
Proceedings of the 2008 ACM symposium on Applied computing, 2008 JUCS - Journal of Universal Computer Science Volume Nr.
Boris Chidlovskii, Loïc Lecerf
+8 more sources
Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications [PDF]
Electronics, 2023 In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed ...
Junhyuk Yang +4 more
openalex +2 more sources
Cooling-System Configurations of a Dual-Stack Fuel-Cell System for Medium-Duty Trucks
Energies, 2023 Presently, hydrogen-fuel-cell medium-duty trucks utilize two or more modular proton exchange membrane fuel-cell stacks due to package space and economic concerns.
Jongbin Woo, Younghyeon Kim, Sangseok Yu
doaj +2 more sources
Stack and Queue Layouts of Posets [PDF]
SIAM Journal on Discrete Mathematics, 1997 Summary: The stacknumber (queuenumber) of a poset is defined as the stacknumber (queuenumber) of its Hasse diagram viewed as a directed acyclic graph. Upper bounds on the queuenumber of a poset are derived in terms of its jumpnumber, its length, its width, and the queuenumber of its covering graph.
Lenwood S. Heath, Sriram V. Pemmaraju
openalex +4 more sources
A study of Through-Silicon-Via impact on the 3D stacked IC layout [PDF]
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009 The technology of through-silicon vias (TSVs) enables fine-grained integration of multiple dies into a single 3-D stack. TSVs occupy significant silicon area due to their sheer size, which has a great effect on the quality of 3-D integrated chips (ICs).
Dae Hyun Kim +2 more
+6 more sources