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Visual Recommendations and Label Layout for Stacked Graphs
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SaVioR: Thwarting Stack-Based Memory Safety Violations by Randomizing Stack Layout
IEEE Transactions on Dependable and Secure Computing, 2022Stack-based memory corruption vulnerabilities have been exploited, allowing attackers to execute arbitrary code and read/write arbitrary memory. Although several solutions have been proposed to prevent memory errors on the stack, they are either limited to a specific type of attack (either spatial or temporal attacks) or cause significant performance ...
Seongman Lee +3 more
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Full stacked layout of analogue cells
IEEE International Symposium on Circuits and Systems, 2003A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors.
U. Gatti, F. Maloberti, V. Liberali
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Stack and Queue Layouts of Directed Acyclic Graphs: Part I
SIAM Journal on Computing, 1993Summary: Stack layouts and queue layouts of undirected graphs have been used to model problems in fault-tolerant computing and in parallel process scheduling. However, problems in parallel process scheduling are more accurately modeled by stack and queue layouts of directed acyclic graphs (dags).
Heath, Lenwood S. +2 more
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Optimum stacked layout for analog CMOS ICs
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 2002A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics, substantially reducing the computational complexity of robust graph algorithms.
E. Malavasi, D. Pandini, V. Liberali
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