Results 151 to 160 of about 108,706 (192)

Space-efficient layouts for block stacking warehouses

IISE Transactions, 2019
In block stacking warehouses, pallets of Stock Keeping Units (SKUs) are stacked on top of one another in lanes on the warehouse floor.
Shahab Derhami, Jeffrey S. Smith, Kevin R. Gue   +2 more
openaire   +1 more source

Automatic generation of transistor stacks for cmos analog layout

1993 IEEE International Symposium on Circuits and Systems, 2002
A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function ...
V. Liberali, E. Malavasi, D. Pandini
openaire   +1 more source

Detecting Stack Layout Corruptions with Robust Stack Unwinding

2016
The stack is a critical memory structure to ensure the correct execution of programs because control flow changes through the data stored in it, such as return addresses and function pointers. Thus the stack has been a popular target by many attacks and exploits like stack smashing attacks and return-oriented programming (ROP).
Yangchun Fu, Junghwan Rhee, Zhiqiang Lin, Zhichun Li, Hui Zhang, Guofei Jiang   +5 more
openaire   +1 more source

Stack and Queue Layouts of Directed Acyclic Graphs: Part II

SIAM Journal on Computing, 1999
Summary: Stack layouts and queue layouts of undirected graphs have been used to model problems in fault tolerant computing and in parallel process scheduling. However, problems in parallel process scheduling are more accurately modeled by stack and queue layouts of directed acyclic graphs (dags).
Heath, Lenwood S., Pemmaraju, Sriram V.
openaire   +2 more sources

Defense against Stack-Based Attacks Using Speculative Stack Layout Transformation

2013
This paper describes a novel technique to defend binaries against intra-frame stack-based attacks, including overflows into local variables, when source code is unavailable. The technique infers a specification of a function’s stack layout, i.e., variable locations and boundaries, and then seeks to apply a combination of transformations, including ...
Benjamin D. Rodes, Anh Nguyen-Tuong, Jason D. Hiser, John C. Knight, Michele Co, Jack W. Davidson   +5 more
openaire   +1 more source

Multi-stack optimization for data-path chip (microprocessor) layout

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible.
W. K. Luk, A. A. Dean
openaire   +1 more source

Stack and Queue Layouts for Toruses and Extended Hypercubes

2010 43rd Hawaii International Conference on System Sciences, 2010
Linear layouts play an important role in many applications including networks and VLSI design. Stack and queue layouts are two important types of linear layouts. We consider the stack number, s(G), and queue number, q(G), for multidimensional k-ary hypercubes and toruses.
S. Bettayeb, M. H. Heydari, L. Morales, I. H. Sudborough   +3 more
openaire   +1 more source

Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors

IEEE Transactions on Electron Devices, 2018
With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation.
Linlin Cai, Wangyong Chen, Gang Du, Xing Zhang, Xiaoyan Liu   +4 more
openaire   +1 more source

Analysis and modeling of layout scaling in silicon integrated stacked transformers

IEEE Transactions on Microwave Theory and Techniques, 2006
The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss).
T. BIONDI, SCUDERI, ANGELO, RAGONESE, EGIDIO, PALMISANO, Giuseppe   +3 more
openaire   +2 more sources

A support-design tool for block-stacking storage system layout

2017
In warehousing system, block stacking is one of the most common storage mode to guarantee high storage density in case of large quantities and limited product variety. Most common applications for block stacking storage are end-of-line warehouses at manufacturing facilities in processing industry (e.g., beverage, bakery, tissue industries).
Accorsi, R., Baruffaldi, G., Galizia, F. G., Manzini, R., Maranesi, F.   +4 more
openaire   +3 more sources