Measurement of Circuit Parasitics of a 200kW SiC based Stack
Applied Power Electronics ConferenceConverters with high power density are becoming necessary in applications such as traction inverters and electric vehicles, where the inverter stage must process power in the range of a few hundred kilowatts. As the inverters are often hard-switched, SiC
Surjakanta Mazumder +5 more
semanticscholar +1 more source
A design for highly robust ALCU-W-PLUG-metallization stack
2016 Pan Pacific Microelectronics Symposium (Pan Pacific), 2016Mission profiles for semiconductor applications are getting more and more challenging regarding electrical and thermo-mechanical robustness of metallization stacks.
V. Hein +4 more
semanticscholar +1 more source
Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors
IEEE Transactions on Electron Devices, 2018With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation.
Linlin Cai +4 more
openaire +1 more source
Analysis and modeling of layout scaling in silicon integrated stacked transformers
IEEE Transactions on Microwave Theory and Techniques, 2006The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss).
T. BIONDI +3 more
openaire +2 more sources
A support-design tool for block-stacking storage system layout
2017In warehousing system, block stacking is one of the most common storage mode to guarantee high storage density in case of large quantities and limited product variety. Most common applications for block stacking storage are end-of-line warehouses at manufacturing facilities in processing industry (e.g., beverage, bakery, tissue industries).
Accorsi, R. +4 more
openaire +3 more sources
Thermal Layout Optimization of Stacked Chip Based on Ant Colony Algorithm
Advanced Materials Research, 2012In this paper, an ant colony algorithm based on mutual information similarity is proposed to solve the stacked chips on the thermal layout optimization. In order to express the mutual information entropy between the optimal path and walking path, a new similarity impact factor is added in the algorithm operators of ant colony algorithm which increases ...
Jiang Guo Jiang +3 more
openaire +1 more source
Optimal Stack Layout Configurations at Automated Container Terminals Using Queuing Network Models
, 2020D. Roy, R. Koster
semanticscholar +1 more source
Thermal layout optimization for 3D stacked multichip modules
Microelectronics Journal, 2023Yanning Chen +4 more
openaire +1 more source
3D Perception Framework for Stacked Container Layout in the Physical Internet
2018The Physical Internet concept was developed to address the current unsustainability problem of logistic systems. The key elements are the encapsulation and the handling of world-standard smart green modular containers (π-containers) throughout an open global logistic infrastructure.
Dong-Seong Kim, Hoa Tran-Dang
openaire +1 more source
A proposed global layout of carbon capture and storage in line with a 2 °C climate target
Nature Climate Change, 2021Yi-Ming Wei, Jia-Ning Kang, Lan-Cui Liu
exaly