Results 261 to 270 of about 7,510 (291)

Stack and Queue Layouts for Toruses and Extended Hypercubes

2010 43rd Hawaii International Conference on System Sciences, 2010
Linear layouts play an important role in many applications including networks and VLSI design. Stack and queue layouts are two important types of linear layouts. We consider the stack number, s(G), and queue number, q(G), for multidimensional k-ary hypercubes and toruses.
Saïd Bettayeb, Mohammad Hossain Heydari, Linda Morales, Ivan Hal Sudborough   +3 more
openaire   +1 more source

Space-efficient layouts for block stacking warehouses

IISE Transactions, 2019
In block stacking warehouses, pallets of Stock Keeping Units (SKUs) are stacked on top of one another in lanes on the warehouse floor.
Shahab Derhami, Jeffrey S. Smith, Kevin R. Gue   +2 more
openaire   +1 more source

Full stacked layout of analogue cells

IEEE International Symposium on Circuits and Systems, 2003
A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors.
U. Gatti, F. Maloberti, V. Liberali
openaire   +1 more source

Automatic generation of transistor stacks for cmos analog layout

1993 IEEE International Symposium on Circuits and Systems, 2002
A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function ...
Valentino Liberali, Enrico Malavasi, Davide Pandini   +2 more
openaire   +1 more source

Optimum stacked layout for analog CMOS ICs

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 2002
A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics, substantially reducing the computational complexity of robust graph algorithms.
E. Malavasi, D. Pandini, V. Liberali
openaire   +1 more source

Smokestack: Thwarting DOP Attacks with Runtime Stack Layout Randomization

2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2019
Todd Austin
exaly   +2 more sources

Multi-stack optimization for data-path chip (microprocessor) layout

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89, 1989
As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible.
Wing K. Luk, Alvar A. Dean
openaire   +1 more source

Stack layout transformation: Towards diversity for securing binary programs

2012 34th International Conference on Software Engineering (ICSE), 2012
exaly   +2 more sources

Analysis and modeling of layout scaling in silicon integrated stacked transformers

IEEE Transactions on Microwave Theory and Techniques, 2006
The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss).
T. BIONDI, SCUDERI, ANGELO, RAGONESE, EGIDIO, PALMISANO, Giuseppe   +3 more
openaire   +2 more sources

An Analytical GPU-Enabled Framework for the Stacked 3D IC Layouts

Journal of Circuits, Systems and Computers
Three-dimensional integrated circuits (3D ICs) have recently garnered significant attention as a potential solution to the challenges posed by interconnect scaling in 2D ICs. However, the inclusion of an extra dimension and the introduction of through-silicon vias (TSVs) for interlayer connections have resulted in a significantly more complex compared
Xin Cheng 0004, Jinjia Zhou, Zhiqiang Zhang, Wenxin Yu 0001   +3 more
openaire   +1 more source