Results 271 to 280 of about 797,630 (345)
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Smokestack: Thwarting DOP Attacks with Runtime Stack Layout Randomization
2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2019Memory corruption vulnerabilities in type-unsafe languages are often exploited to perform a control-flow hijacking attack, in which an attacker uses vulnerabilities to corrupt control data in the program to eventually gain control over the execution of the program.
Misiker Tadesse Aga, Todd Austin
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Defense against Stack-Based Attacks Using Speculative Stack Layout Transformation
Runtime Verification, 2013This paper describes a novel technique to defend binaries against intra-frame stack-based attacks, including overflows into local variables, when source code is unavailable. The technique infers a specification of a function’s stack layout, i.e., variable locations and boundaries, and then seeks to apply a combination of transformations, including ...
Benjamin D. Rodes +5 more
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Optimum stacked layout for analog CMOS ICs
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 2002 A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics, substantially reducing the computational complexity of robust graph algorithms.
E. Malavasi +2 more
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Automatic generation of transistor stacks for cmos analog layout
1993 IEEE International Symposium on Circuits and Systems, 2005 A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function ...
V. Liberali, E. Malavasi, D. Pandini
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Design of an On-Chip Balun With a Minimum Amplitude Imbalance Using a Symmetric Stack Layout
IEEE Transactions on Microwave Theory and Techniques, 2010This study develops a compact balun layout to minimize amplitude imbalance. Three baluns with different metal layers are fabricated using 0.13-?m CMOS technology and their imbalance performance evaluated. Measurement made using eight metal layers in coil windings at a particular layout reveal that the proposed device exhibits minimal amplitude and ...
Szu-Han Lai +3 more
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Analysis and modeling of layout scaling in silicon integrated stacked transformers
IEEE Transactions on Microwave Theory and Techniques, 2006 The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss).
T. Biondi +3 more
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Location specific PV yield and loss simulation based on module stack and layout
2016 International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD), 2016 PV cell and module manufactures optimise their products according to standard test conditions. The key parameter for financing of a solar farm is yield under field or realistic conditions. Field testing modules is expensive and time consuming. Hence we develop a methodology for simulating PV module yield based on the optical, thermal and electrical ...
Andrew Thomson +2 more
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Full stacked layout of analogue cells [PDF]
IEEE International Symposium on Circuits and Systems, 2003 A program for the automatic layout of analogue CMOS cells using the full stacked approach is described. The stacked approach consists of the division of large transistors into several parallel elementary transistors, and of their accommodation in one or more parallel stacks made of the same number of transistors.
Umberto Gatti +2 more
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An Innovative variable layout steam plant for waste heat recovery from marine dual-fuel engines
Ships and Offshore Structures, 2022The paper describes an original Waste Heat Recovery (WHR) variable layout plant to produce steam from the exhaustgases of marine dual-fuel engines. A large part of the steam feeds an electric turbogenerator to improve the ship's energy efficiency.The ...
M. Altosole +3 more
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On Families of Planar DAGs with Constant Stack Number
International Symposium Graph Drawing and Network Visualization, 2021A $k$-stack layout (or $k$-page book embedding) of a graph consists of a total order of the vertices, and a partition of the edges into $k$ sets of non-crossing edges with respect to the vertex order.
M. Nöllenburg, S. Pupyrev
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