Results 281 to 290 of about 797,630 (345)

Stack and Queue Layouts for Toruses and Extended Hypercubes

2010 43rd Hawaii International Conference on System Sciences, 2010
Linear layouts play an important role in many applications including networks and VLSI design. Stack and queue layouts are two important types of linear layouts. We consider the stack number, s(G), and queue number, q(G), for multidimensional k-ary hypercubes and toruses.
Linda Morales, Said Bettayeb, Mohammad Heydari, Ivan Hal Sudborough   +3 more
openaire   +2 more sources

Space-efficient layouts for block stacking warehouses

IISE Transactions, 2019
In block stacking warehouses, pallets of Stock Keeping Units (SKUs) are stacked on top of one another in lanes on the warehouse floor.
Shahab Derhami, Jeffrey S. Smith, Kevin R. Gue   +2 more
openaire   +2 more sources

Stack and Queue Layouts of Directed Acyclic Graphs: Part II

SIAM Journal on Computing, 1999
Summary: Stack layouts and queue layouts of undirected graphs have been used to model problems in fault tolerant computing and in parallel process scheduling. However, problems in parallel process scheduling are more accurately modeled by stack and queue layouts of directed acyclic graphs (dags).
Heath, Lenwood S., Pemmaraju, Sriram V.
openaire   +2 more sources

The Improvement of the Life Time Performance Estimation for Interconnect Stacks in Realistic Layouts

2021 22nd International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2021
The experimental determination of the intrinsic life time of a metallization stack is determined by the used test structures of metal lines and via-metal test structures. The test structure layout is prepared according to the presumption of the failure mechanisms modelled by Black’s Law. The interconnect reliability test structures are optimized.
Verena Hein, Kirsten Weide-Zaage
openaire   +2 more sources

An NVM-Aware Storage Layout for Analytical Workloads

2018 IEEE 34th International Conference on Data Engineering Workshops (ICDEW), 2018
As DRAM is reaching its scalability limit, Non-Volatile Memory (NVM) technologies are moving more and more into focus to meet the requirements of modern database and Big Data systems.
Philipp Götze, S. Baumann, K. Sattler
semanticscholar   +2 more sources

Building Layout Reconstruction in Concealed Human Target Sensing via UWB MIMO Through-Wall Imaging Radar

IEEE Geoscience and Remote Sensing Letters, 2018
This letter is devoted to the layout reconstruction via the ultra-wideband (UWB) through-wall imaging radar under one single observation and simultaneously takes account of the real-time human indication.
Yongping Song, Jun Hu, Ning Chu, T. Jin, Jianwen Zhang, Zhimin Zhou   +5 more
semanticscholar   +1 more source

Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing

International Interconnect Technology Conference, 2018
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduced to
A. Yeoh, A. Madhavan, N. Kybert, S. Anand, J. Shin, M. Asoro, S. Samarajeewa, J. Steigerwald, C. Ganpule, M. Buehler, A. Tripathi, V. Souw, M. Haran, S. Nigam, V. Chikarmane, P. Yashar, T. Mule, Y-H. Wu, K. Lee, M. Aykol, K. Marla, P. Sinha, S. Kirby, H. Hiramatsu, W. Han, M. Mori, M. Sharma, H. Jeedigunta, M. Sprinkle, C. Pelto, M. Tanniru, G. Leatherman, K. Fischer, I. Post, C. Auth   +34 more
semanticscholar   +1 more source

Interface States in Gate Stack of Carbon Nanotube Array Transistors.

ACS Nano
A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high ...
Yifan Liu, Sujuan Ding, Weili Li, Zirui Zhang, Z. Pan, Yumeng Ze, Bing Gao, Yanning Zhang, Chuanhong Jin, L. Peng, Zhiyong Zhang   +10 more
semanticscholar   +1 more source

Optimal layout of stacked graph for visualizing multidimensional financial time series data

Information Visualization, 2021
In the era of big data, the analysis of multi-dimensional time series data is one of the important topics in many fields such as finance, science, logistics, and engineering. Using stacked graphs for visual analysis helps to visually reveal the changing characteristics of each dimension over time.
Yutian He, Hongjun Li
openaire   +2 more sources

Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors

IEEE Transactions on Electron Devices, 2018
With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation.
Linlin Cai, Wangyong Chen, Gang Du, Xing Zhang, Xiaoyan Liu   +4 more
openaire   +2 more sources