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Hybrid Quantum-Classical Algorithm for Robust Optimization via Stochastic-Gradient Online Learning. [PDF]
Lim D, Doriguello JF, Rebentrost P.
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Categorical framework for quantum-resistant zero-trust AI security. [PDF]
Cherkaoui I, Clarke C, Horgan J, Dey I.
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Influences of dynamic and static retrieval cues on memory for events. [PDF]
Smithwick MS +3 more
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2D Materials‐Based Static Random‐Access Memory
Advanced Materials, 2022Abstract2D transition‐metal dichalcogenide semiconductors, such as MoS2 and WSe2, with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)‐based field‐effect transistor (FET) and static random‐access memory (SRAM) cells analyzing the impact of layer thickness reveals that the ...
Lain-Jong Li, Yi Wan, Vita Pi-Ho Hu
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A 128Kb CMOS static random-access memory
IBM Journal of Research and Development, 1991This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip
Jeff L. Chu +2 more
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Testing static and dynamic faults in random access memories
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2003The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed,
Said Hamdioui +2 more
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On design of multiple-valued static random-access-memory
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are ...
Okihiko Ishizuka +2 more
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High-speed GaAs static random-access memory
IEEE Transactions on Electron Devices, 1982An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 V. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions ...
G. Bert +3 more
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Static Random Access Memory Technologies
2009This chapter contains sections titled: Basic SRAM Architecture and Cell Structures SRAM Selection Considerations High Performance SRAMs Advanced SRAM Architectures Low-Voltage SRAMs BiCMOS Technology SRAMs SOI SRAMs Specialty SRAMs This chapter contains sections titled ...
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