Results 251 to 260 of about 16,068 (283)

A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

IEEE Journal of Solid-State Circuits, 2019
A reconfigurable 4096-neuron, 1M-synapse chip in 10-nm FinFET CMOS is developed to accelerate inference and learning for many classes of spiking neural networks (SNNs). The SNN features digital circuits for leaky integrate and fire neuron models, on-chip
Gregory K. Chen, Raghavan Kumar, H. Sumbul, Phil C. Knag, R. Krishnamurthy   +4 more
semanticscholar   +1 more source

Synaptic equalization by anti-STDP

Neurocomputing, 2004
Abstract Experimental evidence has shown that in some neuron types, such as hippocampal CA1 neurons, distally generated excitatory postsynaptic potentials (EPSPs) are scaled up in amplitude compared to more proximally generated EPSPs such that EPSP magnitudes at the soma are approximately equal regardless of the dendritic location of origin. Using an
L. F. Abbott, Clifton C. Rumsey
openaire   +2 more sources

The Trouble with Weight-Dependent STDP

2007 International Joint Conference on Neural Networks, 2007
We fit a weight-dependent STDP rule to the classic data of Bi and Poo (1998), showing that this rule leads to slow learning in a simulation with an integrate-and-fire neuron. The slowness of learning is explained by an inequality between the range of initial weights in the data and the largest relative potentiation.
Thomas Trappenberg, Dominic Standage
openaire   +1 more source

A combinational digital logic approach to STDP

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011
Spike Timing Dependant Plasticity (STDP) is a biologically-based Hebbian reinforcement learning rule for the unsupervised training of synaptic weights in spiking neural networks. We present a low complexity synthetic implementation of STDP using basic combinational digital logic gates.
Cassidy, A., Andreou, A. G., Georgiou, J., Cassidy, A., Andreou, A. G., Georgiou, J.   +5 more
openaire   +3 more sources

Training a Multi-Layer Photonic Spiking Neural Network With Modified Supervised Learning Algorithm Based on Photonic STDP

IEEE Journal of Selected Topics in Quantum Electronics, 2021
We propose a framework for hardware architecture and learning algorithm co-design of multi-layer photonic spiking neural network (SNN). The vertical-cavity surface-emitting laser with an embedded saturable absorber (VCSEL-SA) which contains two ...
S. Xiang, Z. Ren, Yahui Zhang, Z. Song, Xingxing Guo, G. Han, Y. Hao   +6 more
semanticscholar   +1 more source

55nm CMOS Analog Circuit Implementation of LIF and STDP Functions for Low-Power SNNs

International Symposium on Low Power Electronics and Design, 2021
Spiking neural networks (SNNs) demonstrate great potentials to achieve low-power computation for AI applications. SNN uses spike trains, instead of binary bit-steams to encode input and output information, therefore, analog implementation of SNN will ...
Zhitao Yang, Zhujiang Han, Yucong Huang, Terry Tao Ye   +3 more
semanticscholar   +1 more source

Competitive STDP-Based Spike Pattern Learning

Neural Computation, 2009
Recently it has been shown that a repeating arbitrary spatiotemporal spike pattern hidden in equally dense distracter spike trains can be robustly detected and learned by a single neuron equipped with spike-timing-dependent plasticity (STDP) (Masquelier, Guyonneau, & Thorpe, 2008).
Masquelier, Timothée, Guyonneau, Rudy, Thorpe, Simon J   +2 more
openaire   +5 more sources

Neurons Tune to the Earliest Spikes Through STDP

Neural Computation, 2005
Spike timing-dependent plasticity (STDP) is a learning rule that modifies the strength of a neuron's synapses as a function of the precise temporal relations between input and output spikes. In many brains areas, temporal aspects of spike trains have been found to be highly reproducible.
Guyonneau, Rudy, Vanrullen, Rufin, Thorpe, Simon J   +2 more
openaire   +5 more sources

Low-power hybrid memristor-CMOS spiking neuromorphic STDP learning system

IET Circuits Devices Syst., 2021
An electronic circuit that implements a neural network architecture with spike neurons was studied, proposed, and evaluated, primarily considering energy consumption.
Gabriel Maranhão, J. G. Guimarães
semanticscholar   +1 more source

Coexistence of Cell Assemblies and STDP

2009
We implement a model of leaky-integrate-and fire neurons with conductance-based synapses. Neurons are structurally coupled in terms of an ideal cell assembly. Synaptic changes occur through parameterized spike timing-dependent plasticity rules which allows us to investigate the question whether cell assemblies can survive or even be strengthed by such ...
Florian Hauser, Günther Palm, David Bouchain   +2 more
openaire   +2 more sources