Results 141 to 150 of about 181,240 (164)

A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation

IEICE Transactions on Electronics, 2005
This paper describes a speed-oriented ullralow-voltage and low-power SOI circuit technique based on a differential enhancementand depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-V th CMOS circuit block for noncritical path, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to ...
Takakuni Douseki, Toshishige Shimamura, Nobutaro Shibata   +2 more
openaire   +1 more source

Sub 0.5-V bulk-driven winner take all circuit based on a new voltage follower

Analog Integrated Circuits and Signal Processing, 2016
A new solution for a bulk-driven ultra-low-voltage winner take all (WTA) circuit is described. The WTA structure is based on a new voltage follower (VF) circuit which could also be used in other applications as a general purpose precise VF for sub 0.5-V operation.
Tomasz Kulej, Fabian Khateb
openaire   +1 more source

Super stack technique to reduce leakage power for sub 0.5-V supply voltage in VLSI circuits

International Conference on Sustainable Energy and Intelligent Systems (SEISCON 2011), 2011
Leakage current of CMOS circuits has become a major factor in very deep submicron regime. ITRS reports that leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small. In this paper a leakage reduction technique named "Super stack"for sub 0.5-V supply voltage has been ...
T.G. Reddy, K. Suganthi
openaire   +1 more source

A 0.5-V, 3-mW, 54×54-b multiplier with a triple-V/sub th/ CMOS/SIMOX circuit scheme

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345), 2003
K. Fujii, T. Douseki
openaire   +1 more source

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

Analog Integrated Circuits and Signal Processing, 2022
R A Walunj
exaly  

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

IEEE Journal of Solid-State Circuits, 1996
F Silveira, Denis Flandre, P G A Jespers   +2 more
exaly  

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

IEEE Journal of Solid-State Circuits, 2005
K Fukuoka
exaly  

On the effect of technology scaling on variation-resilient sub-threshold circuits

Solid-State Electronics, 2015
Nele Reynders, Wim Dehaene
exaly  

Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits

IEEE Transactions on Electron Devices, 2013
Felice Crupi, Domenico Albano, Massimo Alioto   +2 more
exaly  

Printed Sub‐2 V Gel‐Electrolyte‐Gated Polymer Transistors and Circuits

Advanced Functional Materials, 2010
Mingjing Ha, Jeong Ho Cho, Chris H Kim
exaly