Results 211 to 220 of about 303,436 (267)
Some of the next articles are maybe not open access.

AMULET3i-an asynchronous system-on-chip

Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586), 2002
AMULETSi is the third generation asynchronous ARM-compatible microprocessor subsystem developed at the University of Manchester. It is internally modular, being based around the MARBLE asynchronous on-chip bus, and is also extensible through the addition of conventional clocked synthesizable peripherals via an on-chip synchronous peripheral bus.
Jim D. Garside   +12 more
openaire   +2 more sources

The System-on-a-Chip Lock Cache

Design Automation for Embedded Systems, 2002
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Bilge Saglam Akgul   +1 more
openaire   +2 more sources

A methodology for the verification of a "system on chip"

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1999
This paper summarizes the verification effort of a complex ASIC designated to be an "all in one" ISDN network router. This ASIC is unique because it actually consists of many independent components, called "cores" (including the processor). The integration of these components onto one chip results in an ISOC (Integrated System On a Chip).
Daniel Geist   +9 more
openaire   +1 more source

BIST for systems-on-a-chip

Integration, 1998
Summary: An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of ...
openaire   +2 more sources

Designing a system on a chip

Proceedings of the June 1970 design automation workshop on Design automation - DAC '70, 1970
The rapidly improving capabilities of large scale integrated circuit (LSI) manufacturing technology provide the opportunity for dramatic advances in digital system economy, capacity and flexibility for those who are prepared to modify their design philosophy and procedures to take full advantage of it. This involves much more than the simple first step
openaire   +1 more source

System on Chip

2010
In the previous chapters, we discussed various digital architectures that each present a different trade-off between flexibility and specialization. The trend was from specialized towards more general and more flexible. In this chapter, we complete the discussion with a generic architecture-specialization concept.
openaire   +1 more source

Network-on-Chip Design for Gigascale Systems-on-Chip

2004
The Industrial Information Technology Handbook focuses on existing and emerging industrial applications of IT, and on evolving trends that are driven by the needs of companies and by industry-led consortia and organizations. Emphasizing fast growing areas that have major impacts on industrial automation and enterprise integration, the Handbook covers ...
BERTOZZI, DAVIDE   +2 more
openaire   +5 more sources

On-chip debug support for embedded Systems-on-Chip

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003
This paper presents an on-chip hardware architecture to support application software development for embedded Systems-on-Chips (SoC). This architecture provides debug support for one manufacturer's complete SoC platform. This includes a significant number of 16-bit and 32-bit microcontroller and DSP cores, spanning a multitude of application specific ...
openaire   +1 more source

Systems on a Chip

2004
The growing time-to-market pressure, the need for higher communication bandwidths, and new application areas like wireless communication and the emerging field of ubiquitous computing require a highly increased functionality of microelectronic products and make the development of more complex systems necessary.
Peter Zipf, Manfred Glesner
openaire   +1 more source

FracNoC: A fractal on-chip interconnect architecture for System-on-Chip

2013 International Conference on High Performance Computing & Simulation (HPCS), 2013
Sophisticated on-chip interconnects (OCIs) were recently proposed as a solution to non-scalable shared bus schemes for Systems-on-Chip (SoC) design and implementation. In this paper a new OCI architecture by adapting a fractal topology structure is introduced. Simulations were conducted to compare this topology with two common OCIs, 2D Mesh, and Torus,
Chariete, A.   +4 more
openaire   +2 more sources

Home - About - Disclaimer - Privacy