Results 91 to 100 of about 3,147,688 (366)
Designing Memristive Materials for Artificial Dynamic Intelligence
Key characteristics required of memristors for realizing next‐generation computing, along with modeling approaches employed to analyze their underlying mechanisms. These modeling techniques span from the atomic scale to the array scale and cover temporal scales ranging from picoseconds to microseconds. Hardware architectures inspired by neural networks
Youngmin Kim, Ho Won Jang
wiley +1 more source
Response errors explain the failure of independent-channels models of perception of temporal order
Independent-channels models of perception of temporal order (also referred to as threshold models or perceptual latency models) have been ruled out because two formal properties of these models (monotonicity and parallelism) are not borne out by data ...
Miguel A García-Pérez +1 more
doaj +1 more source
This article presents the artificial synapse based on strontium titanate thin films via spin‐coating followed by forming gas annealing to introduce oxygen vacancies. Characterizations (X‐ray photoelectron spectroscopy, electron paramagnetic resonance, Ultraviolet photoelectron spectroscopy (UPS)) confirm increased oxygen vacancies and downward energy ...
Fandi Chen +16 more
wiley +1 more source
Abstract This research focuses on addressing the privacy issues in healthcare advancement monitoring with the rapid establishment of the decentralised communication system in the Internet of Medical Things (IoMT). An integrated blockchain homomorphic encryption standard with an in‐build supervised learning‐based smart contract is designed to improvise ...
Chandramohan Dhasarathan +7 more
wiley +1 more source
A Comparison of some recent Task-based Parallel Programming Models [PDF]
The need for parallel programming models that are simple to use and at the same time efficient for current ant future parallel platforms has led to recent attention to task-based models such as Cilk++, Intel TBB and the task concept in OpenMP version 3.0.
Brorsson, Mats +2 more
core +1 more source
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
Enhancement of GPU-accelerated smoothed particle hydrodynamics (SPH) method with dynamic parallelism
An innovative GPU programming architecture leveraging CUDA Dynamic Parallelism (CDP) is introduced in this study, aiming to enhance the computational efficiency of Smoothed Particle Hydrodynamics (SPH) simulations.
Liwen Xue, Shenglong Gu, Songdong Shao
doaj +1 more source
Towards Task-Parallel Reductions in OpenMP
Reductions represent a common algorithmic pattern in many scientific applications. OpenMP* has always supported them on parallel and worksharing constructs. OpenMP 3.0’s tasking constructs enable new parallelization opportunities through the annotation of irregular algorithms.
Alex Duran +14 more
openaire +4 more sources
Automatic Parallelization: Executing Sequential Programs on a Task-Based Parallel Runtime
There are billions of lines of sequential code inside nowadays' software which do not benefit from the parallelism available in modern multicore architectures.
Cabral, Bruno +3 more
core +1 more source
Configurable Kernel Map Implementation in Memristor Crossbar for Convolution Neural Network
A configurable kernel map implementation using a memristor crossbar array is presented. The crossbar array area can be configured based on the number of read cycles per inference, which directly affects the inference speed. The algorithm underlying this scheme is described, and convolutional neural network operations are experimentally validated using ...
Gyeonghae Kim +3 more
wiley +1 more source

