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Incremental test pattern generation

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 2002
Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with
Sang-Hoon Song, Larry L. Kinney
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Automatic test pattern generation with branch testing

IEEE Transactions on Computers, 1991
The authors present a test algorithm for finite state machines called branch testing. Based on branch testing, a design-for-test (DFT) method is proposed. Comparisons to other DFT methods show the method to be competitive relative to circuit overhead.
Rafic Z. Makki   +2 more
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Test Pattern Selection for Defect-Aware Test

2011 Asian Test Symposium, 2011
With shrinking of LSIs, the diversification of defective mode becomes a critical issue. As a result, test patterns for stuck-at faults and transition faults are insufficient to detect such defects. N-detection tests have been known as an effective way for achieving high defect coverage, but the large number of test pattern counts is the problem.
Yoshinobu Higami   +4 more
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Patterns of syphilis testing in the elderly

Journal of General Internal Medicine, 1992
To evaluate the frequency of inconsistencies in the use of laboratory tests for syphilis among the elderly in an acute care setting.Retrospective medical record review.Academic medical center.All patients 60 years of age and older who had: 1) positive tests for syphilis and no lumbar puncture performed (n = 71), 2) lumbar punctures performed and no ...
B J, Naughton, M B, Moran
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On Test Patterns for Cloud Applications

2016 International Conference on Frontiers of Information Technology (FIT), 2016
Software testing is an important aspect for the quality of software. Different levels of experience, types of application and needs enforce differences in performing testing activity for same features of applications. Testing as an activity within a development house usually includes testing of recurrent situation e.g., testing of security features etc.
Sidra Siddiqui, Tamim Ahmed Khan
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Testing Patterns in Action: Designing a Test-Pattern-Based Suite

International Review on Computers and Software (IRECOS), 2015
Design patterns constitute a revolution in the field of software engineering, as they emphasize the importance of reuse and its impact on the software process and the software product quality. A special type of design patterns is testing patters; these can be used in the testing phase to reduce redundancy, save time and resources and provide an ...
Bouchaib Falah   +2 more
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Test patterns

2012
These patterns are native format patterns for a number of displays that support the corresponding horizontal and vertical input pixel counts. They were initially developed by Edward F. Kelley when he was with NIST, with contributions from Joe Miseli. Thanks also to Michael H. Brill for the concept of the Color Inversion Pattern (see files CINV01_...)
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Testing Multiclass Pattern Discrimination

2012 Second International Workshop on Pattern Recognition in NeuroImaging, 2012
Machine learning is increasingly adopted in neuroimaging-based neuroscience studies. The paradigm of predicting the stimuli provided to the subject from the concurrent brain activity is known as "brain decoding" and accurate predictions support the hypothesis that the brain activity encodes those stimuli.
Emanuele Olivetti   +2 more
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Methods for testing subblock patterns

Statistics and Computing, 1999
A number of statistical tests have been recommended over the last twenty years for assessing the randomness of long binary strings used in cryptographic algorithms. Several of these tests include methods of examining subblock patterns. These tests are the uniformity test, the universal test and the repetition test.
Helen Gustafson   +3 more
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Test pattern generation with restrictors

Proceedings of IEEE International Test Conference - (ITC), 2002
This paper extends state-of-the-art ATPG systems by including constraints, called restrictors, on the allowable values of the bits of a test vector. Such restrictors often occur in "real-world" circuits where certain bit positions of a test vector have to take on a particular value (e.g.
M. H. Konijnenburg   +2 more
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