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A combinator library for the design of railway track layouts
Journal of Functional Programming, 2011Abstract In the design of railway track layouts, there are only a small number of geometric configurations that are used in practice, and a number of constraints as to how those configurations can be fitted together to create a whole layout. In order to solve these problems, we construct a Haskell combinator library.
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An Area Layout-Based MAP Estimation for Indoor Target Tracking
2010 IEEE 72nd Vehicular Technology Conference - Fall, 2010To improve the performance of a received signal strength indication (RSSI)-based maximum likelihood (ML) location estimation method, we have so far proposed an area layout-based maximum a posterirori (MAP) location estimation method for a stationary target.
Daisuke Anzai, Shinsuke Hara
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A Television News Graphical Layout Analysis Method Using Eye Tracking
2012 16th International Conference on Information Visualisation, 2012This paper presents an analysis method used to evaluate the graphical layout of Television (TV) News. With the data gathered from an eye tracker, it is possible to discern viewers' main focus of attention. However, in the case of video media, the visualisation tools of eye tracking software are insufficient for this discernment.
Rui Rodrigues 0002 +2 more
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2003
Graph drawing problems originate from diverse application domains. In some, such as software engineering and cartography, graphs are required to be visualized or drawn in ways that are easy to read and understand. In others, such as VLSI design, graphs are required to be laid out while satisfying some physical constraint. For example, when a drawing is
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Graph drawing problems originate from diverse application domains. In some, such as software engineering and cartography, graphs are required to be visualized or drawn in ways that are easy to read and understand. In others, such as VLSI design, graphs are required to be laid out while satisfying some physical constraint. For example, when a drawing is
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Reliability performance of different layouts of wide metal tracks
2014 IEEE International Reliability Physics Symposium, 2014For industrial and automotive applications a 0.35μm aluminium CMOS process is one of the common used technologies. An increasing demand on extended operating conditions must be fulfilled especially for high current carrying metal lines. A new design concept is to modify the shape of these lines.
Jorg Kludt +4 more
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Using eye tracking to investigate graph layout effects
2007 6th International Asia-Pacific Symposium on Visualization, 2007Graphs are typically visualized as node-link diagrams. Although there is a fair amount of research focusing on crossing minimization to improve readability, little attention has been paid on how to handle crossings when they are an essential part of the final visualizations. This requires us to understand how people read graphs and how crossings affect
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An Efficient Polynomial-Time Algorithm for Three-track Gate Matrix Layout
The Computer Journal, 1994Gate Matrix Layout (GML) is a combinatorial optimization problem that arises in several VLSI layout styles. It is known to be equivalent to other important in combinational graph theory including vertex separation and pathwidth. While the general problem is N P-complete, when the relevant parameter is fixed, the decision problem can be solved in ...
Nancy G. Kinnersley +1 more
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Railway Track Layout Asset Reader Using Computer Vision
2025 4th International Conference on Applied Artificial Intelligence and Computing (ICAAIC)Shinu Abhi
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Experimental Study on Dynamic Map Information Layout Based on Eye Tracking
2020In the GIS system interface, the map module occupies more than 90% of the interface size, which is the focus of the GIS interface design. There are a large number of targets, target signs, target trajectories and other information on the map. The layout of various information is crowded and overlapped, making it difficult for users to search and ...
Jiapei Ren +2 more
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Memory Layouts in the ALICE Track Reconstruction
In high performance computing, we strive for algorithms on large arrays to be as performant as possible. However, the performance of such an algorithm is also affected by the memory layout of these arrays. The most natural memory layout is Array-of-Structures (AoS), which performs well for strided access patterns and for large classes.Rietmann, Oliver Gregor, Chen, Jolly
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