Results 11 to 20 of about 21,846 (260)

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

open access: yesInternational Journal of Reconfigurable Computing, 2009
Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world.
Diana Göhringer   +3 more
doaj   +1 more source

Influence of Noisy Environment on the Speech Recognition Rate Based on the Altera FPGA [PDF]

open access: yesEngineering and Technology Journal, 2013
This paper introduce an approach to study the effects of different levels of environment noise on the recognition rate of speech recognition systems, which are not used any type of filters to deal with this issue.
Eyad I. Abbas, Alaa Abdulhussain Refeis
doaj   +1 more source

Compiler Optimization on Instruction Scheduling for a Specialized Real-Time Floating Point Soft-Core Processor

open access: yesAdvances in Electrical and Computer Engineering, 2019
This paper presents the authors' research in the field of specialized optimizing assembly language compilers for embedded real-time soft-core processor systems on FPGAs.
KIRCHHOFF, M., WAGNER, L., FENGLER, W.
doaj   +1 more source

Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems

open access: yesJournal of Low Power Electronics and Applications, 2019
This discussion develops a theoretical analog architecture framework similar to the well developed digital architecture theory. Designing analog systems, whether small or large scale, must optimize their architectures for energy consumption.
Jennifer Hasler
doaj   +1 more source

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure

open access: yesIEEE Access, 2021
Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance ...
Ba-Anh Dao   +5 more
doaj   +1 more source

Performance Analyses of a RAIM Algorithm for Kalman Filter with GPS and NavIC Constellations

open access: yesSensors, 2021
This paper evaluates the performance of an integrity monitoring algorithm of global navigation satellite systems (GNSS) for the Kalman filter (KF), termed KF receiver autonomous integrity monitoring (RAIM).
Susmita Bhattacharyya
doaj   +1 more source

Optical character recognition on heterogeneous SoC for HD automatic number plate recognition system

open access: yesEURASIP Journal on Image and Video Processing, 2018
Automatic number plate recognition (ANPR) systems are becoming vital for safety and security purposes. Typical ANPR systems are based on three stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR ...
Ali Farhat   +6 more
doaj   +1 more source

Performance Enhancement of GNSS/MEMS-IMU Tightly Integration Navigation System Using Multiple Receivers

open access: yesIEEE Access, 2020
Global Navigation Satellite System (GNSS) and Inertial Navigation System (INS) are the most commonly used navigation systems. They both have unique advantages and disadvantages.
Zhenshu Zhu, Changhui Jiang, Yuming Bo
doaj   +1 more source

Computing the singular value decomposition on a distributed system of vector processors [PDF]

open access: yesParallel Computing, 1989
The two-sided Jacobi algorithm of \textit{G. E. Forsythe} and \textit{P. Henrici} [Trans. Am. Math. Soc. 94, 1-23 (1960; Zbl 0092.325)] is implemented on a LCAP system consisting of a ring of vector processors. Two block versions are compared on a series of random test matrices, and it is demonstrated that the computation is nearly perfectly sped up ...
openaire   +2 more sources

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor [PDF]

open access: yesJournal of Electronic Testing, 2002
A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other ...
Abhijit Jas, Nur A. Touba
openaire   +2 more sources

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