Results 11 to 20 of about 22,809 (305)

Evaluating the Vector Supercomputer SX-Aurora TSUBASA as a Co-Processor for In-Memory Database Systems

Datenbank-Spektrum, 2019
In-memory column-store database systems are state of the art for the efficient processing of analytical workloads. In these systems, data compression as well as vectorization play an important role. Currently, the vectorized processing is done using regular SIMD (Single Instruction Multiple Data) extensions of modern processors.
Johannes Pietrzyk, Dirk Habich, Patrick Damme, Erich Focht, Wolfgang Lehner   +4 more
core   +5 more sources

Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications [PDF]

, 2023
The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance ...
Marimon Illana, Joan, Mendoza Escobar, Jonnatan, Cristal Kestelman, Adrián, Vargas Valdivieso, Ivan, Cabre Olive, Joan, Palomar Pérez, Óscar, Rojas Morales, Carlos, Ruíz Ramírez, Abraham Josafat, Hernández Calderón, César Alejandro, Kovac, Mario, Kovac, Mate, Minervini Minervini, Francesco, Olivieri, Mauro, Unsal, Osman Sabri, Moll Echeto, Francisco de Borja, Reggiani, Enrico, Khoirunisya, Lina, Valero Cortés, Mateo, Quiroga Esparza, Josué Vladimir, Pavón Rivera, Julián, Figueras Bagué, Roger, Bouhali, Mustapha, González Trejo, Alberto, Dragic, Leon   +23 more
core   +1 more source

Reusable Verification Environment for a RISC-V Vector Accelerator [PDF]

, 2023
This paper presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors.
Díaz, Ivan, Quiroga, Josue, Yano, Henrique, Ali, Asif, Genovese, Roberto Ignacio, Sommez, Nehir, Palomar Pérez, Óscar, JImenez, Victor, Rodriguez, Mario, Dominguez, Marc   +9 more
core   +1 more source

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor [PDF]

Journal of Electronic Testing, 2002
A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other ...
Abhijit Jas, Nur A. Touba
openaire   +2 more sources

Low-power VLSI implementation of the inner receiver for OFDM-based WLAN systems [PDF]

, 2008
In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems.
Koushik Maharatna, Milo¿ Krstic, Eckhard Grass, Troya, Alfonso, Kraemer, Rolf, Jagdhold, Ulrich, Maharatna, Koushik, Krstic, Milos, Grass, Eckhard, Ulrich Jagdhold, Rolf Kraemer, Alfonso Troya   +11 more
core   +1 more source

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

International Journal of Reconfigurable Computing, 2009
Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world.
Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker   +3 more
doaj   +1 more source

Influence of Noisy Environment on the Speech Recognition Rate Based on the Altera FPGA [PDF]

Engineering and Technology Journal, 2013
This paper introduce an approach to study the effects of different levels of environment noise on the recognition rate of speech recognition systems, which are not used any type of filters to deal with this issue.
Eyad I. Abbas, Alaa Abdulhussain Refeis
doaj   +1 more source

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure

IEEE Access, 2021
Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance ...
Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham   +5 more
doaj   +1 more source

A C++-embedded Domain-Specific Language for programming the MORA soft processor array [PDF]

, 2010
MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM).
Purohit, S., Margala, M., W. Vanderbauwhede, Vanderbauwhede, W., S. R. Chalamalasetti, Chalamalasetti, S.R., S. Purohit, M. Margala   +7 more
core   +1 more source

Compiler Optimization on Instruction Scheduling for a Specialized Real-Time Floating Point Soft-Core Processor

Advances in Electrical and Computer Engineering, 2019
This paper presents the authors' research in the field of specialized optimizing assembly language compilers for embedded real-time soft-core processor systems on FPGAs.
KIRCHHOFF, M., WAGNER, L., FENGLER, W.
doaj   +1 more source