Results 221 to 230 of about 106,049 (265)

Distributed vector architectures

Journal of Systems Architecture, 2000
A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory.
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VAX vector architecture

Proceedings of the 17th annual international symposium on Computer Architecture - ISCA '90, 1990
The VAX Architecture has been extended to include an integrated, register-based vector processor. This extension allows both high-end and low-end implementations and can be supported with only small changes by VAX/VMS and VAX/ULTRIX operating systems. The extension is effectively exploited by the new vectorizing capabilities of VAX FORTRAN.
D. Bhandarkar, R. Brunner
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Vectorization of Architectural Floor Plans

2019 Twelfth International Conference on Contemporary Computing (IC3), 2019
This paper proposes a method to vectorize the architectural floor plans by recognizing the graphic primitives used in such drawings. The method consists of thin and thick layer separation of the input image, followed by the identification of thin lines, arcs, and circles.
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Supporting matrix operations in vector architectures

Proceedings Sixth International Parallel Processing Symposium, 2003
Many elementary numerical algorithms involve not only vector operations but also matrix operations. Today's vector processors only support vector operations, and execute matrix operations in terms of vector operations, because they can not access matrix operands in one instruction. This will lead to poor sustained performances of vector machines.
Hua Bi, Wolfgang K. Giloi
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A Simulation Study of Decoupled Vector Architectures

The Journal of Supercomputing, 1999
Decoupling techniques can be applied to a vector processor, resulting in a large increase in performance of vectorizable programs. We simulate a selection of the Perfect Club and Specfp92 benchmark suites and compare their execution time on a conventional single port vector architecture with that of a decoupled vector architecture. Decoupling increases
Roger Espasa, Mateo Valero
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Towards an open architecture for vector GIS

Computers & Geosciences, 2006
A range of open source software tools are now available to the Geographical Information Systems (GIS) analyst. However these tools are not necessarily interoperable and rarely significantly interoperable with proprietary systems. The open architectures, which have been developed for web-oriented systems, together with those proposed by the Open ...
Robert I. Dunfey, Bruce M. Gittings, James K. Batcheller   +2 more
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3D on-chip memory for the vector architecture

2009 IEEE International Conference on 3D System Integration, 2009
Vector supercomputers play an important roll in a high performance computing area because vector systems can achieve a high computational efficiency for large scale scientific applications. The most important factor of a vector supercomputer is its high memory bandwidth between the processor and the off-chip main memory.
Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi   +3 more
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A VLSI implementation of the VAX vector architecture

Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage, 2002
A single-board implementation of the VAX vector architecture is described. The vector processor can be divided into three separate function units: the vector controller, implemented as a single chip; the arithmetic pipelines, implemented by four pairs of chips; and the load/store unit, implemented by one chip.
David M. Fenwick, John Redford, Tim Stanley, Douglas D. Williams   +3 more
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VLSI architecture for motion vector quantization

IEEE Transactions on Consumer Electronics, 2003
The paper present a novel VLSI architecture for block-matching operations based on motion vector quantizers (MVQs). Since the distribution of the MVQ check point locations is irregular, the usual VLSI architectures for regular block-matching processes may not be effective for the hardware implementation of the MVQ.
Wen-Jyi Hwang, Chien-Min Ou, Wen-Ming Lu, Chun-Fu Lin   +3 more
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A vector coprocessor architecture for embedded systems

2011 International SoC Design Conference, 2011
We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs.
Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Makiko Ito, Yoshio Hirose, Hiromasa Takahashi   +6 more
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