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Generative AI Assertions in UVM-Based System Verilog Functional Verification [PDF]

Systems
This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal ...
Valentin Radu, Diana Dranga, Catalin Dumitrescu, Alina Iuliana Tabirca, Maria Cristina Stefan   +4 more
doaj   +2 more sources

Detraque: Dynamic execution tracing techniques for automatic fault localization of hardware design code. [PDF]

PLoS ONE, 2022
In an error-prone development process, the ability to localize faults is a crucial one. Generally speaking, detecting and repairing errant behavior at an early stage of the development cycle considerably reduces costs and development time.
Jiang Wu, Zhuo Zhang, Jianjun Xu, Jiayu He, Xiaoguang Mao, Xiankai Meng, Panpan Li   +6 more
doaj   +2 more sources

Best Practices for Compact Modeling in Verilog-A

IEEE Journal of the Electron Devices Society, 2015
Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in ...
Colin C. McAndrew, Geoffrey J. Coram, Kiran K. Gullapalli, J. Robert Jones, Laurence W. Nagel, Ananda S. Roy, Jaijeet Roychowdhury, Andries J. Scholten, Geert D. J. Smit, Xufeng Wang, Sadayuki Yoshitomi   +10 more
doaj   +2 more sources

Neuromorphic photonic circuit modeling in Verilog-A

APL Photonics, 2022
One of the significant challenges in neuromorphic photonic architectures is the lack of good tools to simulate large-scale photonic integrated circuits.
Jagmeet Singh, Hugh Morison, Zhimu Guo
exaly   +2 more sources

Optoelectronic device library containing multiple Verilog-A models [PDF]

Scientific Reports
The advancement of the optoelectronic fusion industry has escalated the demands for optoelectronic simulation, yet a comprehensive model library remains unavailable for chip designers.
Guanliang Chen, Zhigang Song, Xinhe Zheng   +2 more
doaj   +2 more sources

VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005
François Pêcheux, Christophe Lallement, Alain Vachoux   +2 more
exaly   +3 more sources

Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits [PDF]

International Journal of Electronics and Telecommunications, 2021
This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog- AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model
Billel Smaani, Yacin Meraihi, Fares Nafa, Mohamed Salah Benlatreche, Hamza Akroum, Saida Latreche   +5 more
doaj   +1 more source

Aplikasi Perancang Abstraksi Verilog Mesin Keadaan Terbatas Otomatis

Semesta Teknika, 2021
Saat ini, hampir semua perangkat elektronik menggunakan prosesor di dalamnya. Dalam sebuah prosesor, terdapat bagian control unit yang berfungsi mengatur operasi dari komponen-komponen di dalam prosesor.
Fairuz Azmi
doaj   +1 more source

Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays

Energies, 2021
Two design flows of the Petri net-based cyber-physical systems oriented towards implementation in an FPGA are presented in the paper. The first method is based on the behavioural description of the system. The control part of the cyber-physical system is
Remigiusz Wisniewski
doaj   +1 more source

Open Platform for Digital Design Learning on FPGA-based Systems

Revista Elektrón, 2020
In embedded systems a wide variety of applications can be solved or approached using different technologies, such as microcontrollers, FPGA, Systems on Chip (SoC), among others.
Martín Alejandro Heredia, Facundo Santiago Larosa, Ramiro Adrián Ghignone, Federico Alejandro Vázquez Saraullo, Hernán Pablo Mendes Gouveia   +4 more
doaj   +1 more source