Detraque: Dynamic execution tracing techniques for automatic fault localization of hardware design code. [PDF]
PLoS ONE, 2022 In an error-prone development process, the ability to localize faults is a crucial one. Generally speaking, detecting and repairing errant behavior at an early stage of the development cycle considerably reduces costs and development time.
Jiang Wu +6 more
doaj +2 more sources
Neuromorphic photonic circuit modeling in Verilog-A
APL Photonics, 2022 One of the significant challenges in neuromorphic photonic architectures is the lack of good tools to simulate large-scale photonic integrated circuits.
Jagmeet Singh +8 more
doaj +2 more sources
VerilogAE: An Open Source Verilog-A Compiler for Compact Model Parameter Extraction
IEEE Journal of the Electron Devices Society, 2020 This article introduces a new open-source Verilog-A compiler, VerilogAE, purpose-built to ease compact model parameter extraction. VerilogAE retrieves all model equations, their dependencies, and relevant model parameters that are defined in a Verilog-A ...
Pascal Kuthe +2 more
doaj +2 more sources
Optoelectronic device library containing multiple Verilog-A models [PDF]
Scientific ReportsThe advancement of the optoelectronic fusion industry has escalated the demands for optoelectronic simulation, yet a comprehensive model library remains unavailable for chip designers.
Guanliang Chen +2 more
doaj +2 more sources
VerilogEval: Evaluating Large Language Models for Verilog Code Generation [PDF]
arXiv.org, 2023 The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specifically for evaluating LLM performance in the context of Verilog code ...
Mingjie Liu +3 more
semanticscholar +1 more source
VeriGen: A Large Language Model for Verilog Code Generation [PDF]
ACM Trans. Design Autom. Electr. Syst., 2023 In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by automatically completing partial Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on Verilog
Shailja Thakur +6 more
semanticscholar +1 more source
Benchmarking Large Language Models for Automated Verilog RTL Code Generation [PDF]
Design, Automation and Test in Europe, 2022 Automating hardware design could obviate a signif-icant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description language to model and design digital systems, thus generating Verilog code is a
Shailja Thakur +7 more
semanticscholar +1 more source
A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation [PDF]
arXiv.org, 2023 Innovative Electronic Design Automation (EDA) solutions are important to meet the design requirements for increasingly complex electronic devices.
Enrique Dehaerne +3 more
semanticscholar +1 more source
Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits [PDF]
International Journal of Electronics and Telecommunications, 2021 This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog- AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model
Billel Smaani +5 more
doaj +1 more source
Aplikasi Perancang Abstraksi Verilog Mesin Keadaan Terbatas Otomatis
Semesta Teknika, 2021 Saat ini, hampir semua perangkat elektronik menggunakan prosesor di dalamnya. Dalam sebuah prosesor, terdapat bagian control unit yang berfungsi mengatur operasi dari komponen-komponen di dalam prosesor.
Fairuz Azmi
doaj +1 more source