A Strategy Language for Testing Register Transfer Level Logic [PDF]
, 2009 The development of modern ICs requires a huge investment in RTL verification. This is a reflection of brisk release schedules and the complexity of contemporary chip designs.
Katelman, Michael, Meseguer, Jos??
core
Just-In-Time Compilation for Verilog: A New Technique for Improving the FPGA Programming Experience
International Conference on Architectural Support for Programming Languages and Operating Systems, 2019 FPGAs offer compelling acceleration opportunities for modern applications. However compilation for FPGAs is painfully slow, potentially requiring hours or longer. We approach this problem with a solution from the software domain: the use of a JIT.
Eric Schkufza +2 more
semanticscholar +1 more source
High‐Accuracy Frequency Detection and Analysis via Adaptive Frequency Standard Tracking
IET Signal Processing, Volume 2025, Issue 1, 2025.Precise frequency detection is one of the key problems to be solved in a high‐accuracy transfer of time and frequency. The solution to this problem is helpful in improving the precision of the phase noise measurement, atomic frequency standard, and time synchronization, which plays a strong role in the whole precision measurement physics fields. A high‐
Baoqiang Du +3 more
wiley +1 more source
Perancangan dan Implementasi Algoritma DES untuk Mikroprosesor Enkripsi dan Dekripsi pada FPGA
Jurnal Teknologi dan Sistem Komputer, 2015 Seiring dengan semakin luasnya penerapan teknologi komputasi di sekitar kita, menjadikan informasi menjadi sangat mudah dan cepat untuk disebarkan. Kita dapat mengakses informasi dan data-data yang kita butuhkan dengan mudah. Namun permasalahan yang kita
Imaduddin Amrullah Muslim +2 more
doaj +1 more source
Parameter Extraction for the PSPHV LDMOS Transistor Model
IEEE Journal of the Electron Devices Society, 2020 This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating.
Kejun Xia +2 more
doaj +1 more source
A Verilog HDL digital architecture for delay calculation [PDF]
, 2007 A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source.
Chacón-Rodríguez, A. +3 more
core
Large-signal model of the Metal-Insulator-Graphene diode targeting RF applications
, 2019 We present a circuit-design compatible large-signal compact model of metal-insulator-graphene (MIG) diodes for describing its dynamic response for the first time.
Hamed, Ahmed +6 more
core +1 more source
Design of Low‐Power, High‐Precision, and Lightweight Image Recognition System for Multiple Scenes
Active and Passive Electronic Components, Volume 2025, Issue 1, 2025.Aiming at the existing handwritten digit recognition systems with low recognition accuracy, high system power consumption, and high hardware resource consumption, this paper proposes a low‐power, high‐precision, and lightweight handwritten digit recognition hardware acceleration scheme for multiscenario based on FPGA.
Gangfeng Yang +5 more
wiley +1 more source
Triple frame buffer FPGA implementation
HardwareX, 2019 This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes.
James Williams, Ilya Mikhelson
doaj
Eternal-Thing 3.0: Mixed-Mode SoC for Energy Harvesting System Towards Sustainable IoT
IEEE AccessThe power requirement in IoT is essential to fulfill the energy demand of the power-hungry sensors at end nodes. The use of fixed batteries restricts sustainability and makes the system costly.
Saswat Kumar Ram +4 more
doaj +1 more source