Results 121 to 130 of about 24,676 (260)

Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation

, 1996
Brown, R. B., Marques-Silva, J. P., Riepe, M. A., Sakallah, K. A.   +3 more
core   +1 more source

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog [PDF]

Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan   +6 more
openalex   +1 more source

VERILOR: A Verilog-A Model of Lorentzian Spectra for Simulating Trap-related Noise in CMOS Circuits

, 2021
Angeliki Tataridou, G. Ghibaudo, Christoforos Theodorou   +2 more
openalex   +2 more sources

Universal Memory Automaton and Automated Verilog HDL Code Generation for a Cache Coherency Snooping Protocol

, 2020
Matthias Fertig
openalex   +1 more source

Enabling Model-Based Design for Real-Time Spike Detection. [PDF]

IEEE Open J Eng Med Biol
Di Florio M, Bornat Y, Care M, Rosa Cota V, Buccelli S, Chiappalone M.   +5 more
europepmc   +1 more source

Design and Implementation of High-Speed Variable Point Pipelined FFT Processor for OFDM System using Verilog

, 2019
V. Brunda
openalex   +1 more source

Implementation of 64-Bits Radix - 8 IFFT for Computation Speed by IDIF using Verilog

, 2020
Bipin Kumar, M.Naveen Reddy, Vamshi Kollipara, B. Rajesh   +3 more
openalex   +1 more source

Implementation of Individual and Combined In-loop Filters for HEVC and AVC Video Coding Standards on ASIC Platform Using 32 nm Technology Library

Applications of Modelling and Simulation
High Efficiency Video Coding (HEVC) and Advanced Video Coding (AVC), the developed international standards for video compression, offer significantly better video compression efficiency.
Siu Hong Loh, Aw Yong Pik Yee, Jia Jia Sim, Kim Ho Yeap   +3 more
doaj  

A field-programmable gate array based on wafer-scale 2D semiconductor. [PDF]

Natl Sci Rev
Sun Q, Ao M, Dong X, Shi K, Gou S, Zhu Y, Zhang Z, Zhang J, Hu Y, Sun Z, Chen X, Wang L, Bao W, Zhou P.   +13 more
europepmc   +1 more source

Realization of Advanced Peripheral Bus(APB) Protocol using Verilog

B. Ravi Kumar, Katte Srisha, Boppana Akhila   +2 more
openalex   +2 more sources