Results 141 to 150 of about 37,772 (288)

Compact Modeling of Two-Dimensional Field-Effect Biosensors. [PDF]

Sensors (Basel), 2023
Pasadas F, El Grour T, G Marin E, Medina-Rull A, Toral-Lopez A, Cuesta-Lopez J, G Ruiz F, El Mir L, Godoy A.   +8 more
europepmc   +1 more source

Simulation of 16 bit ALU using Verilog-hdl [PDF]

, 2017
Mayank Mittal
openalex   +1 more source

A Normalized Model of a Microelectromechanical Relay Calibrated by Laser-Doppler Vibrometry. [PDF]

Micromachines (Basel), 2022
Marvin J, Jang M, Contreras D, Spencer M.   +3 more
europepmc   +1 more source

VERILOG DASTURLASH TILI YORDAMIDA DASTURLASH [PDF]

, 2023
Umidjon Zaripovich Narziyev
openalex   +1 more source

Engineering of An Assertion-based PSLSimple-Verilog Dynamic Verifier by Alternating Automata

, 2008
Naiyong Jin, Chengjie Shen, Jun Chen, Taoyong Ni   +3 more
openalex   +1 more source

A Comprehensive Large Signal, Small Signal, and Noise Model for IGZO Thin Film Transistor Circuits. [PDF]

IEEE Trans Electron Devices, 2023
Vatsyayan R, Dayeh SA.
europepmc   +1 more source

Fault Injection and Test Approach for Behavioural Verilog Designs using the Proposed RASP-FIT Tool [PDF]

, 2019
Abdul Rafay Khatri, Ali Hayek, Josef Börcsök   +2 more
openalex   +1 more source

Parallel Processing of Sobel Edge Detection on FPGA: Enhancing Real-Time Image Analysis. [PDF]

Sensors (Basel)
Ravichandran S, Su HK, Kuo WK, Dhanasekaran D, Mahalingam M, Yang JP.   +5 more
europepmc   +1 more source

IMPLEMENTATION OF RSA KEY GENERATION BASED ON RNS USING VERILOG

, 2012
M VISHAK, N. SHANKARAIAH
openalex   +1 more source

Implementation of VLSI Based Efficient Lossless EEG Compression Architecture using Verilog HDL

, 2021
G. Premalatha, J. Mohana, Suvitha P.S, J Manikandan   +3 more
openalex   +1 more source