Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model
Zizhen Jiang, S.S. Wong
openalex +1 more source
Design and simulation of artificial retinal stimulation IC with switched capacitor using Si nanowire optical properties. [PDF]
Han S, Kim T, Kim C, Lee S.
europepmc +1 more source
Teaching computer architecture by designing and simulating processors from their bits and bytes. [PDF]
Doğan M, Öztoprak K, Tolun MR.
europepmc +1 more source
Modified vedic multiplier architecture using Nikhilam and Karatsuba algorithms with hybrid adders for enhanced performance. [PDF]
A S, A S.
europepmc +1 more source
An Efficient Power Delay Product of ZigBee Transmitter Using Verilog HDL
Raja Prakasha Rao Pasala +1 more
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An FPGA-Based Reconfigurable Accelerator for Real-Time Affine Transformation in Industrial Imaging Heterogeneous SoC. [PDF]
Zhang Y +5 more
europepmc +1 more source
Free software support for compact modelling with Verilog-A [PDF]
A. Bürmen +6 more
doaj +1 more source
A deterministic neuromorphic architecture with scalable time synchronization. [PDF]
Li C, Imam N, Manohar R.
europepmc +1 more source
FPGA-based low-light image enhancement using Retinex algorithm and coarse-grained reconfigurable architecture. [PDF]
Munaf S, Bharathi A, Jayanthi AN.
europepmc +1 more source

