Results 151 to 160 of about 24,676 (260)

Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model

, 2014
Zizhen Jiang, S.S. Wong
openalex   +1 more source

Design and simulation of artificial retinal stimulation IC with switched capacitor using Si nanowire optical properties. [PDF]

Sci Prog
Han S, Kim T, Kim C, Lee S.
europepmc   +1 more source

Teaching computer architecture by designing and simulating processors from their bits and bytes. [PDF]

PeerJ Comput Sci
Doğan M, Öztoprak K, Tolun MR.
europepmc   +1 more source

Modified vedic multiplier architecture using Nikhilam and Karatsuba algorithms with hybrid adders for enhanced performance. [PDF]

Sci Rep
A S, A S.
europepmc   +1 more source

An Efficient Power Delay Product of ZigBee Transmitter Using Verilog HDL

, 2017
Raja Prakasha Rao Pasala, B. Rajendra Naik   +1 more
openalex   +1 more source

An FPGA-Based Reconfigurable Accelerator for Real-Time Affine Transformation in Industrial Imaging Heterogeneous SoC. [PDF]

Sensors (Basel)
Zhang Y, Chen D, Ruan H, Jia H, Liu Y, Luo Y.   +5 more
europepmc   +1 more source

Free software support for compact modelling with Verilog-A [PDF]

Informacije MIDEM
A. Bürmen, T. Tuma, I. Fajfar, J. Puhan, Ž. Rojec, M. Kunaver, S. Tomažič   +6 more
doaj   +1 more source

A deterministic neuromorphic architecture with scalable time synchronization. [PDF]

Nat Commun
Li C, Imam N, Manohar R.
europepmc   +1 more source

AREA EFFICIENT UART DESIGN USING VERILOG HDL

Dr.Ravi Bolimera, K. Prasanna, Ranga Deepshika, Shanigarapu saikiran, Sappidi Mallikarjun Reddy   +4 more
openalex   +2 more sources

FPGA-based low-light image enhancement using Retinex algorithm and coarse-grained reconfigurable architecture. [PDF]

Sci Rep
Munaf S, Bharathi A, Jayanthi AN.
europepmc   +1 more source