Results 161 to 170 of about 24,676 (260)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs [PDF]

Juxin Niu, Yuxin Du, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan   +5 more
openalex   +1 more source

Cryo-SIMPLY: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. [PDF]

Nanomaterials (Basel)
Moposita T, Garzón E, Teman A, Lanuzza M.   +3 more
europepmc   +1 more source

A Compact Memristor Model Based on Physics-Informed Neural Networks. [PDF]

Micromachines (Basel)
Lee Y, Kim K, Lee J.
europepmc   +1 more source

BetterV: Controlled Verilog Generation with Discriminative Guidance [PDF]

Z. F. Pei, Hui‐Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu   +4 more
openalex   +1 more source

Multi-stage decimation with hybrid CIC-polyphase filtering for IoT gateway sample rate conversion. [PDF]

Sci Rep
Pinjerla S, Rao SS, Reddy PC.
europepmc   +1 more source

Fully automated processor chip design: motivation, challenges and future directions. [PDF]

Natl Sci Rev
Zhang R, Guo J, Cheng S, Chen Y.
europepmc   +1 more source

An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys’ Galaxy Platform

, 2012
Mistry, Jatin N., Myers, James
core  

Machine learning-powered compact modeling of stochastic electronic devices using mixture density networks. [PDF]

Sci Rep
Hutchins J, Alam S, Rampini DS, Oripov BG, McCaughan AN, Aziz A.   +5 more
europepmc   +1 more source

Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog

, 2018
Harish M S M S, D Jayadevappa
openalex   +2 more sources

Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding. [PDF]

PLoS One
Sakthivel R, Vijayalakshmi C, Vanitha M, AboRas KM, Abdelfattah WM, Ghadi YY, Rami Reddy C.   +6 more
europepmc   +1 more source