VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs [PDF]
Juxin Niu +5 more
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Cryo-SIMPLY: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. [PDF]
Moposita T +3 more
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A Compact Memristor Model Based on Physics-Informed Neural Networks. [PDF]
Lee Y, Kim K, Lee J.
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BetterV: Controlled Verilog Generation with Discriminative Guidance [PDF]
Z. F. Pei +4 more
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Multi-stage decimation with hybrid CIC-polyphase filtering for IoT gateway sample rate conversion. [PDF]
Pinjerla S, Rao SS, Reddy PC.
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Fully automated processor chip design: motivation, challenges and future directions. [PDF]
Zhang R, Guo J, Cheng S, Chen Y.
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Machine learning-powered compact modeling of stochastic electronic devices using mixture density networks. [PDF]
Hutchins J +5 more
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Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog
Harish M S M S, D Jayadevappa
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Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding. [PDF]
Sakthivel R +6 more
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