Results 181 to 190 of about 24,676 (260)

A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors. [PDF]

ACS Nano
Zhao G, Wen W, Liao K, Coquet P, Wang X, Huang M, Tay BK.   +6 more
europepmc   +1 more source

Low power and high-speed quadrate node upset tolerant latch design using CNTFET. [PDF]

Sci Rep
Asiya S, S SK.
europepmc   +1 more source

DynBlock: dynamic data encryption with Toffoli gate for IoT. [PDF]

Sci Rep
Haq M, Shoukat IA, Naushad A, Jafri MR, Sandhu M, Khan AU, Shin H.   +6 more
europepmc   +1 more source

Exploring memory synchronization and performance considerations for FPGA platform using the high-abstracted OpenCL framework: Benchmarks development and analysis. [PDF]

PLoS One
Almomany A, Jarrah A, Sutcu M.
europepmc   +1 more source

BlinkBoard: Guiding and monitoring circuit assembly for synchronous and remote physical computing education. [PDF]

HardwareX
Bianchi A, Moon KJ, Dementyev A, Je S.
europepmc   +1 more source

Bendable non-silicon RISC-V microprocessor. [PDF]

Nature
Ozer E, Kufel J, Prakash S, Raisiardali A, Kindgren O, Wong R, Ng N, Jausseran D, Alkhalil F, Kong D, Hills G, Price R, Reddi VJ.   +12 more
europepmc   +1 more source

3-bit Constant-time Synchronous Binary Counter (Verilog)

Dr. P. Dhilip Kumar, Ashwin S, Harini D, Miruthula S, Jai Abinav T
openalex   +1 more source

Low-Power-Management Engine: Driving DDR Towards Ultra-Efficient Operations. [PDF]

Micromachines (Basel)
Liu Z, Li Y, Zeng X.
europepmc   +1 more source

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks. [PDF]

Sci Rep
Das H, Schuman C, Chakraborty NN, Rose GS.   +3 more
europepmc   +1 more source