Results 11 to 20 of about 24,676 (260)
Dual Neural Network Framework with SPICE Integration for Fast and Accurate Transistor Modeling
Advanced Intelligent SystemsNeural network (NN)‐based compact transistor models have recently emerged as a promising solution to simplify device modeling. However, they are often deployed and evaluated standalone due to the lack of compatibility with existing simulation program ...
Rodion Novkin, Hussam Amrouch
doaj +2 more sources
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Implementation of serial peripheral interface slave device based on uncommitted logic arrays [PDF]
Serbian Journal of Electrical EngineeringMicrocontrollers and microprocessors link to peripheral devices (sensors, converters, transceivers, memory modules) via communication interfaces. One of the most widespread interfaces is the Serial Peripheral Interface (SPI), characterized by ...
Sinyukin Alexander +4 more
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A Formal Executable Semantics of Verilog [PDF]
, 2010 This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ...
Katelman, Michael +3 more
core +1 more source
VerilogAE: An Open Source Verilog-A Compiler for Compact Model Parameter Extraction
IEEE Journal of the Electron Devices Society, 2020 This article introduces a new open-source Verilog-A compiler, VerilogAE, purpose-built to ease compact model parameter extraction. VerilogAE retrieves all model equations, their dependencies, and relevant model parameters that are defined in a Verilog-A ...
Pascal Kuthe +2 more
doaj +1 more source
Mind the (synthesis) gap: examining where academic FPGA tools lag behind industry [PDF]
, 2015 Firstly, we present VTR-to-Bitstream v2.0, the latest version of our open-source toolchain that takes Verilog input and produces a packed, placed— and now routed—solution that can be programmed onto the Xilinx commercial FPGA architecture.
Hung, E
core +1 more source
Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
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Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors [PDF]
, 2009 Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-
DeHon, André, Kapre, Nachiket
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Design and verification of HDLC data frame parallel search and decapsulation module
Dianzi Jishu Yingyong, 2022 The HDLC signal link is the high level data link control(HDLC) developed by the international organization for standar- dization(ISO). The article follows the HDLC standard data link layer specification, uses the hardware description language Verilog HDL
Qian Yong, Liu Wei
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International Journal of Reconfigurable Computing, 2022 In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board.
Peter Jamieson +4 more
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