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Toward an ion-based large-scale integrated circuit: design, simulation, and integration. [PDF]

Commun Eng
Edri Fraiman N, Sabbagh B, Yossifon G, Fish A.   +3 more
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Optimization techniques for distributed verilog simulation

, 2008
Lijun Li
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Verilog — A Tutorial Introduction

1991
Digital systems are highly complex. At their most detailed level, they may consist of millions of elements, as would be the case if we viewed a system as a collection of logic gates or pass transistors. From a more abstract viewpoint, these elements may be grouped into a handful of functional components such as cache memories, floating point units ...
Donald E. Thomas, Philip R. Moorby
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Verilog-AMS-PAM

Proceedings of the great lakes symposium on VLSI, 2012
Current Verilog-AMS system level modeling does not capture the physical design (layout) information of the target design as it is meant to be fast behavioral simulation only. Thus, the results of behavioral simulation can be very inaccurate. In this paper a paradigm shift of the current trend is presented that integrates layout level information (with ...
Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov   +3 more
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Optimizing compiled Verilog

International Verilog HDL Conference, 2002
While optimization of traditional programming languages is reasonably well understood, optimization of hardware description languages is much less so. Hardware description languages provide both a different set of problems and a different set of opportunities for optimization.
R. Allen, M. McNamara
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The Verilog Procedural Interface for the Verilog Hardware Description Language

Proceedings. IEEE International Verilog HDL Conference, 2002
The Verilog Procedural Interface is a new C programming interface for the Verilog Hardware Description Language. Different Verilog HDL based tools such as simulators, synthesizers, timing analyzers, and parsers could support this interface for applications which extend the tool's functionality.
C. Dawson, S.K. Pattanam, D. Roberts
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Verilog and VHDL

1992
Verilog is a hardware description language originally designed by Gateway for a proprietary simulation product. This company later merged with Cadence Design Systems, Inc. Since then, Verilog has been known and used as the language of the Cadence digital simulator.
Jean-Michel Bergé, Alain Fonkoua, Serge Maginot, Jacques Rouillard   +3 more
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