Results 201 to 210 of about 24,676 (260)

An RTL Verilog processor

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), 2003
This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time.
H. Jamal, S. Khan, F. Hameed, S. Saeed, M. Pasha   +4 more
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Incrementally recompiling Verilog

Proceedings. 1995 IEEE International Verilog HDL Conference, 2002
One of the frustrations frequently encountered by users of high level design languages is the large amount of time required to process small changes in the design. This frustration is particularly acute in the final stage of hardware design when using a hardware description language like Verilog or VHDL. Since hardware models tend to be quite large and
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Verilog (Part 2)

2017
In Chap. 5, Verilog was presented as a way to describe the behavior of concurrent systems. The modeling techniques presented were appropriate for combinational logic because these types of circuits have outputs dependent only on the current values of their inputs.
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Verilog (Part 1)

2017
Based on the material presented in Chap. 4, there are a few observations about logic design that are apparent. First, the size of logic circuitry can scale quickly to the point where it is difficult to design by hand. Second, the process of moving from a high-level description of how a circuit works (e.g., a truth table) to a form that is ready to be ...
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Power MOSFET Verilog modelling

2016 12th IEEE International Symposium on Electronics and Telecommunications (ISETC), 2016
Power MOSFETs are electronic devices used for modern switches. The complexity of mixed-signal system-on-chip using power MOSFETs has increased. Advanced analog and digital interfaces, tough requirements for their safety and reliability impose new advanced methodologies for their simulations.
Lidia Dobrescu, Daniel Tudora, Dragos Dobrescu   +2 more
openaire   +1 more source

Verilog nonblocking assignments demystified

Proceedings International Verilog HDL Conference and VHDL International Users Forum, 2002
Nonblocking assignments are an important construct to accurately model hardware both for behavioral and RTL simulation; however, there are many misunderstandings surrounding how nonblocking assignments work. This paper examines many of the misunderstandings surrounding nonblocking assignments and how nonblocking assignments are appropriately used in ...
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Incremental Verilog Parser

2023 International Symposium of Electronics Design Automation (ISEDA), 2023
Xiangli Chen, Yuehua Meng, Gang Chen
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System Verilog Assertions

2013
An assertion is simply a check against the specification of your design that you want to make sure never violates. If the specs are violated, you want to see a failure.
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Verilog Constructs and Combinational Design-I

2021
An efficient RTL design always uses minimum number of logic gates. This chapter discusses about the combinational logic design using the synthesizable Verilog constructs, also discusses about the practical and real-life scenarios, and is useful while implementing combinational designs.
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Formalising VERILOG

ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), 2002
null He Jifeng, null Zhu Huibiao
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