Results 221 to 230 of about 37,772 (288)

Multi-Car Parking System Using Verilog

2022 International Conference on Wireless Communications Signal Processing and Networking (WiSPNET), 2022
Parking slots in closed spaces like shopping malls and multistoried building etc. usually find it difficult to keep track of free space and required manual labor to do the same.
R Rishikesh Mahadevan, A. A., P. M, R. R.   +3 more
semanticscholar   +1 more source

A small, but important, concurrency problem in Verilog's semantics? (Work in progress)

International Conference on Formal Methods and Models for Co-Design, 2022
Despite its many flaws, Verilog is today both the most popular hardware design language and a popular language for communication between hardware development tools.
Andreas Lööw
semanticscholar   +1 more source

The Verilog Procedural Interface for the Verilog Hardware Description Language

Proceedings. IEEE International Verilog HDL Conference, 2002
The Verilog Procedural Interface is a new C programming interface for the Verilog Hardware Description Language. Different Verilog HDL based tools such as simulators, synthesizers, timing analyzers, and parsers could support this interface for applications which extend the tool's functionality.
S.K. Pattanam, D. Roberts, C. Dawson
openaire   +2 more sources

Verilog-A and Verilog-AMS provides a new dimension in modeling and simulation

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474), 2002
Verilog-A provides a new dimension in modeling, design and simulation capability for analog and mixed signal electronic systems. Previously, analog simulation has been based upon Spice, which is a very effective simulation environment based on primitives such as transistors, resistors, and capacitors.
T. Cassagnes, I. Miller
openaire   +2 more sources

Lutsig: a verified Verilog compiler for verified circuit development

Certified Programs and Proofs, 2021
We report on a new verified Verilog compiler called Lutsig. Lutsig currently targets (a class of) FPGAs and is capable of producing technology mapped netlists for FPGAs. We have connected Lutsig to existing Verilog development tools, and in this paper we
Andreas Lööw
semanticscholar   +1 more source

Assertion & Functional Coverage Driven Verification of AMBA Advance Peripheral Bus Protocol Using System Verilog

2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2021
Design and Verification of the AMBA based Advanced Peripheral bus is presented in this paper. Verification environment is constructed using the System Verilog, it has features like Functional coverage, Assertion coverage, constrained Randomization and ...
P. Dwivedi, Neha Mishra, Amit Singh-Rajput   +2 more
semanticscholar   +1 more source

Design of UART Using Verilog And Verifying Using UVM

2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021
Verification of a complex VLSI design is a tedious process. Verification of Integrated Circuits using System Verilog lacks the reusability of the test bench of the environment.
B. Priyanka, M. Gokul, A. Nigitha., J.T Poomica.   +3 more
semanticscholar   +1 more source

Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification

International SoC Design Conference, 2021
Chisel is a hardware design method that uses Scala programming language, and exploits many useful features of Scala like object-oriented programming and functional programming.
Jaekyung Im, Seokhyeong Kang
semanticscholar   +1 more source

BetterV: Controlled Verilog Generation with Discriminative Guidance

International Conference on Machine Learning
Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process.
Zehua Pei, Hui-Ling Zhen, M. Yuan, Yu Huang, Bei Yu   +4 more
semanticscholar   +1 more source

An RTL Verilog processor

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), 2003
This paper presents a processor that efficiently executes Verilog code written at Register Transfer Level (RTL). It is a RISC type processor that performs the parallel execution of multiple procedural blocks of Verilog HDL. This results in a very significant saving of simulation time.
Shoab A. Khan, Habibullah Jamal, S. Saeed, M. Pasha, F. Hameed   +4 more
openaire   +2 more sources