Results 231 to 240 of about 37,772 (288)

Verilog and VHDL

1992
Verilog is a hardware description language originally designed by Gateway for a proprietary simulation product. This company later merged with Cadence Design Systems, Inc. Since then, Verilog has been known and used as the language of the Cadence digital simulator.
Jean-Michel Bergé, Serge Maginot, Alain Fonkoua, Jacques Rouillard   +3 more
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Analog design with Verilog-A

Proceedings of Meeting on Verilog HDL (IVC/VIUF'97), 2002
Verilog-A is a language to describe analog behavior. It is an extension to the IEEE 1364 Verilog Hardware Description Language (HDL) specification. A complete definition of the Verilog-A hardware description language, as proposed by the analog Technical Subcommittee of Open Verilog International (OVI), can be found in the Verilog-A Language Reference ...
D. FitzPatrick, R. Aisola, I. Miller
openaire   +2 more sources

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

AAAI Conference on Artificial Intelligence
Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors.
Chia-Tung Ho, Haoxing Ren, Brucek Khailany   +2 more
semanticscholar   +1 more source

Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction

arXiv.org
We explore the use of Large Language Models (LLMs) to generate high-quality Register-Transfer Level (RTL) code with minimal human interference. The traditional RTL design workflow requires human experts to manually write high-quality RTL code, which is ...
Hanxian Huang, Zhenghan Lin, Zixuan Wang, Xin Chen, Ke Ding, Jishen Zhao   +5 more
semanticscholar   +1 more source

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

arXiv.org
Despite the significant progress made in code generation with large language models, challenges persist, especially with hardware description languages such as Verilog.
Mingjie Liu, Yun-Da Tsai, Wenfei Zhou, Haoxing Ren   +3 more
semanticscholar   +1 more source

AI-Powered Neural Network Verification: System Verilog Methodologies for Machine Learning in Hardware

Journal of Artificial Intelligence General science (JAIGS) ISSN:3006-4023
 This research focuses on verifying neural network models using System Verilog, with two primary applications: visual edge detection and neuron behavior modeling.
Prashis Raghuwanshi
semanticscholar   +1 more source

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation

International Conference on Computer Aided Design
Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large language models, garnering significant attention.
Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang   +11 more
semanticscholar   +1 more source

A Verilog to C compiler

Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), 2002
This paper describes a compiler which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native-mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics of Verilog, and also performs logic minimisation.
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PNOC: Implementation on Verilog for FPGA [PDF]

2013 9th International Conference on Innovations in Information Technology (IIT), 2013
Network on Chip (NoC) architectures provide a very efficient means for performance enhancement in digital circuits. The paper describes a NoC implementation that is specifically targeted towards FPGA based designs. Our implementation is based on a lightweight circuit-switched architecture called programmable NoC (PNoC).
Falah Awwad, Osman Hasan, U. Mushtaq
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Microprocessor Component Design in Verilog

2021
This chapter gives an overview of the part of the Verilog hardware description language used in later chapters. As with most languages, we start with lexical preliminary and then discuss data types, operations, and statements of the Verilog language. Coding tips, additional help, and further reading complete the chapter.
openaire   +2 more sources