Results 251 to 260 of about 37,772 (288)

System Verilog Assertions

2013
An assertion is simply a check against the specification of your design that you want to make sure never violates. If the specs are violated, you want to see a failure.
openaire   +2 more sources

Rapid Simulation of Photonic Integrated Circuits using Verilog-A Compact Models

Midwest Symposium on Circuits and Systems, 2019
With the advent of silicon-based integration of photonics, there is a growing interest in the electronic circuits community to develop hybrid electronic-photonic integrated systems.
Md Jubayer Shawon, V. Saxena
semanticscholar   +1 more source

On the Scalability of Parallel Verilog Simulation

2009 International Conference on Parallel Processing, 2009
As a consequence of Moore’s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective.
Wei Zhang, Sina Meraji, Carl Tropper
openaire   +2 more sources

Introduction to the Verilog Language

1997
In this chapter we will look at some of the formal definitions of the Verilog language: identifiers, white space, comments, numbers, text macros, modules, value set, and strengths.
openaire   +2 more sources

On code coverage measurement for Verilog-A

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940), 2004
In order to verify the integration of digital circuits and analog circuits in a SOC design, HDL-A languages are proposed to describe analog circuits such that they can be simulated together with the digital circuits described in HDL code. For digital circuits, coverage-driven approach has been widely used to verify the quality of HDL designs.
Mu-Shun Lee, Yuan-Bin Sha, Chien-Nan Jimmy Liu   +2 more
openaire   +2 more sources

HDL Modeling with VERILOG

1996
This chapter introduces in detail the hardware description language VERILOG. The reader is enabled to create his or her own hardware models and to fully understand the Interpreter Model and the Coarse Structure Model of the RISC processor TOOBSIE. The introduction is conceived as both a course and a reference.
openaire   +2 more sources

A Proof-Producing Translator for Verilog Development in HOL

FME Workshop on Formal Methods in Software Engineering, 2019
We present an automatic proof-producing translator targeting the hardware description language Verilog. The tool takes a circuit represented as a HOL function as input, translates the input function to a Verilog program and automatically proves a ...
Andreas Lööw, Magnus O. Myreen
semanticscholar   +1 more source

Short Introduction to VERILOG

1996
This chapter will give the reader a first overview of the hardware description language VERILOG by several small examples. Together with the extensive introduction in Chapter 11, which can be used whenever needed in parallel to the remainder of the book, and with the training simulator VeriWell on the enclosed disk, all foundations and concepts for ...
openaire   +2 more sources

Effective Design and Implementation of AMBA AHB Bus Protocol using Verilog

International Conferences on Information Science and System, 2019
The computer's performance is intensely reliant on bus interconnect design. An ineffectively designed system bus can interfere with the transmission of guidelines and the information between the memory and processor or between the peripheral gadgets and ...
L. Deeksha, B. Shivakumar
semanticscholar   +1 more source

Verilog at the RTL Level

2004
This chapter gives a quick introduction to the Verilog language utilized throughout this book. The ideas presented in this text are designed to get the reader acquainted with the coding style and methodology utilized. There are many enhancements to Verilog that provide high-level constructs that make coding easier for the designer.
openaire   +2 more sources