Results 21 to 30 of about 37,772 (288)
MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation [PDF]
2024 IEEE LLM Aided Design Workshop (LAD)Large Language Models (LLMs) have recently shown promise in streamlining hardware design processes by encapsulating vast amounts of domain-specific data.
Yongan Zhang +4 more
semanticscholar +1 more source
Mind the (synthesis) gap: examining where academic FPGA tools lag behind industry [PDF]
, 2015 Firstly, we present VTR-to-Bitstream v2.0, the latest version of our open-source toolchain that takes Verilog input and produces a packed, placed— and now routed—solution that can be programmed onto the Xilinx commercial FPGA architecture.
Hung, E
core +1 more source
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs [PDF]
ICCDRecently, the use of large language models (LLMs) for software code generation, e.g., C/C++ and Python, has proven a great success. However, LLMs still suffer from low syntactic and functional correctness when it comes to the generation of register ...
Mingzhe Gao +7 more
semanticscholar +1 more source
ASimOV: A Framework for Simulation and Optimization of an Embedded AI Accelerator
Micromachines, 2021 Artificial intelligence algorithms need an external computing device such as a graphics processing unit (GPU) due to computational complexity. For running artificial intelligence algorithms in an embedded device, many studies proposed light-weighted ...
Dong Hyun Hwang +3 more
doaj +1 more source
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation [PDF]
, 2018 Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new approach to model them in Verilog-A HDL with the help of a powerful tool: TCAD simulation. Besides, to the best of our knowledge, this is
Carmona Galán, Ricardo +3 more
core +1 more source
International Journal of Reconfigurable Computing, 2022 In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board.
Peter Jamieson +4 more
doaj +1 more source
A Multi-Expert Large Language Model Architecture for Verilog Code Generation [PDF]
2024 IEEE LLM Aided Design Workshop (LAD)Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation. However, the existing approaches are limited in terms of the quality of the generated Verilog code.
Bardia Nadimi, Hao Zheng
semanticscholar +1 more source
A Hardware Descriptive Approach to Beetle Antennae Search
IEEE Access, 2020 Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms.
Zongcheng Yue +5 more
doaj +1 more source
RTL-DEVS: HDL Design and Simulation Methodology for DEVS Formalism-Based Simulation Tool
Telecom, 2022 DEVS (Discrete Event System Specification) is widely used in modeling and simulation fields to design, validate, and implement complex response systems.
Bo-Seung Kwon +4 more
doaj +1 more source
Circuit modeling of a MEMS varactor including dielectric charging dynamics [PDF]
, 2016 Electrical models for MEMS varactors including the effect of dielectric charging dynamics are not available in commercial circuit simulators. In this paper a circuit model using lumped ideal elements available in the Cadence libraries and a basic Verilog-
Andrade Miceli, Dennis +5 more
core +2 more sources