Best Practices for Compact Modeling in Verilog-A
IEEE Journal of the Electron Devices Society, 2015 Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in ...
Colin C. McAndrew +10 more
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A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route
Journal of Low Power Electronics and Applications, 2021 This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement ...
Gaetano Palumbo, Giuseppe Scotti
doaj +1 more source
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors [PDF]
, 2009 Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE model-
DeHon, André, Kapre, Nachiket
core +2 more sources
Development of Intelligent Building Energy-saving Temperature Control System Based on FPGA [PDF]
E3S Web of Conferences, 2019 The ideal energy-saving building should meet the environmental quality of living space in different seasons with the least energy consumption. The indoor temperature of the building is an important consideration. However, most temperature control systems
Gao Li, Zhang Runmei, Zhang Guangbin
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Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs [PDF]
IEEE Symposium on Field-Programmable Custom Computing Machines, 2019 This paper introduces a fully free and open source software (FOSS) architecture-neutral FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement, routing, and bitstream generation. Currently, this flow supports two commercially
David Shah +5 more
semanticscholar +1 more source
Making Money from Exploiting Schumpeterian Opportunities: John Sanguinetti and the Electronic Design Automation Industry [PDF]
Technology Innovation Management Review, 2012 Accounts of the effect that John Sanguinetti’s two companies had on the market for integrated circuit design languages were used to gain insights on how to profit from the exploitation of Schumpeterian opportunities.
Arthur Low
doaj
Design Automation and Implementation of Machine Learning Classifier Chips
IEEE Access, 2020 This paper presents a novel framework that automates the creation of a trained-classifier integrated circuit from a dataset. The framework accepts a dataset in a comma-separated value format and performs several processing steps to create a trained model.
Ratshih Sayed +3 more
doaj +1 more source
Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits
Journal of Low Power Electronics and Applications, 2022 This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced compact MOSFET (ACM) model and was implemented ...
Cristina Missel Adornes +3 more
doaj +1 more source
Device modelling for bendable piezoelectric FET-based touch sensing system [PDF]
, 2016 Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point.
Dahiya, Ravinder +4 more
core +1 more source
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs [PDF]
Asia and South Pacific Design Automation ConferenceLarge Language Models (LLMs) have been applied to various hardware design tasks, including Verilog code generation, EDA tool scripting, and RTL bug fixing.
Manar Abdelatty +2 more
semanticscholar +1 more source