Results 31 to 40 of about 24,676 (260)

Design Automation and Implementation of Machine Learning Classifier Chips

IEEE Access, 2020
This paper presents a novel framework that automates the creation of a trained-classifier integrated circuit from a dataset. The framework accepts a dataset in a comma-separated value format and performs several processing steps to create a trained model.
Ratshih Sayed, Haytham Azmi, Amin M. Nassar, Heba Shawkey   +3 more
doaj   +1 more source

Modeling of CMOS devices and circuits on flexible ultrathin chips [PDF]

, 2017
The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications.
Dahiya, Ravinder, Gupta, Shoubhik, Heidari, Hadi, Vilouras, Anastasios   +3 more
core   +1 more source

Fast, non-monte-carlo estimation of transient performance variation due to device mismatch [PDF]

, 2010
This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency.
Horowitz, M., Jones, K., Kim, J.
core   +1 more source

Апаратна реалізація потокового обчислювача логарифму для даних в форматі з фіксованою комою

Mìkrosistemi, Elektronìka ta Akustika, 2020
В роботі розглянуто існуючі підходи до обчислення логарифму. Запропоновано параметризовану апаратну реалізацію потокового обчислювача логарифму за основою 2 для даних в форматі з фіксованою комою, що дозволяє визначати точність обчислень, а також ...
Yaroslav O. Hordiienko, Anton Yu. Varfolomieiev, Ievgen V. Korotkyi   +2 more
doaj   +1 more source

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing [PDF]

, 2018
LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow ...
Alvarez, Carlos, Bautista, Leonardo, Becker, Tobias, Billung-Meyer, Gunnar, Carpenter, Paul, Christmann, Wolfgang, Cristal, Adrian, De La Cruz, Raul, Dubhashi, Devdatt, Etsion, Yoav, Felber, Pascal, Fetzer, Christof, Gaydadjiev, Georgi, Göttel, Christian, Hadar, Elad, Hagemeyer, Jens, Jimenez, Daniel, Jungeblut, Thorsten , Kaiser, Martin , Klawonn, Frank, Krupop, Stefan, Kucza, Nils, Madonar, Sergi, Martorell, Xavier, Mihklafi, Amani, Mudge, Trevor, Mudge, Trevor, Pasin, Marcelo, Pericàs, Miquel, Pnevmatikatos, Dionisios N., Porrmann, Mario , Port, Oron, Rocha, Isabelly, Salami, Behzad, Salomonsson, Hans, Schiavoni, Valerio, Trancoso, Pedro, Unsal, Osman S., vor dem Berge, Micha   +38 more
core   +1 more source

V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

IEEE Open Journal of Circuits and Systems
This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and ...
Chao Wang, Yicong Shao, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li   +9 more
doaj   +1 more source

Hardware/Software Partitioning in Verilog [PDF]

, 2002
نقترح في هذه الورقة نهجًا جبريًا لتقسيم الأجهزة/البرامج في Verilog HDL. نستكشف مجموعة من القوانين الجبرية لبرامج Verilog، والتي نصمم منها مجموعة من القواعد الجبرية القائمة على بناء الجملة لإجراء تقسيم الأجهزة/البرامج. لغة التحديد المشترك ولغات وصف الأجهزة والبرامج المستهدفة هي مجموعات فرعية محددة من Verilog، والتي تحققنا بنجاح من صحة عملية التقسيم عن ...
Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang   +3 more
openaire   +2 more sources

Design of Novel Algorithm and Architecture for Gaussian Based Color Image Enhancement System for Real Time Applications

, 2013
This paper presents the development of a new algorithm for Gaussian based color image enhancement system. The algorithm has been designed into architecture suitable for FPGA/ASIC implementation. The color image enhancement is achieved by first convolving
A.K. Jain, D. Jobson, H. Cheng, M. Zhang
core   +1 more source

BDAQ53, a versatile pixel detector readout and test system for the ATLAS and CMS HL-LHC upgrades

, 2020
BDAQ53 is a readout system and verification framework for hybrid pixel detector readout chips of the RD53 family. These chips are designed for the upgrade of the inner tracking detectors of the ATLAS and CMS experiments.
Daas, Michael, Dieter, Yannick, Dingfelder, Jochen, Frohne, Markus, Giakoustidis, Georgios, Hemperek, Tomasz, Hinterkeuser, Florian, Hügging, Fabian, Janssen, Jens, Krüger, Hans, Pohl, David-Leon, Rymaszewski, Piotr, Standke, Mark, Vogt, Marco, Wang, Tianyang, Wermes, Norbert   +15 more
core   +1 more source

Ternary Content‐Addressable Memory Using One Capacitor and One Nanoelectromechanical Memory Switch for Data‐Intensive Applications

Advanced Intelligent Systems, EarlyView.
A charge‐domain ternary content‐addressable memory using one capacitor one nanoelectromechanical memory switch (1C‐1N TCAM) is proposed for energy‐efficient, high‐reliability computations. Integrated with the back‐end‐of‐line process, the 1C‐1N TCAM leverages the air gap capacitance to achieve a high capacitance ratio and ternary functionality.
Jin Wook Lee, Changha Kim, Geun Tae Park, Seung Hun Baek, Myeong Su Shin, Woo Young Choi   +5 more
wiley   +1 more source