Description styles of fault-tolerant finite state machines for unmanned aerial vehicles
Радіоелектронні і комп'ютерні системиThe subject matter of this article is finite state machines (FSMs), which are used as control devices in unmanned aerial vehicles (UAVs). The goal of this study is to develop description styles for fault-tolerant FSMs in hardware description languages ...
Valery Salauyou
doaj +1 more source
A High permormance hardware architecture for an sad reuse based hierarchical motion estimation algorithm for H.264 video coding [PDF]
, 2005 In this paper, we present a high performance and low cost hardware architecture for real-time implementation of an SAD reuse based hierarchical motion estimation algorithm for H.264 / MPEG4 Part 10 video coding.
Ates, Hasan F. +5 more
core
Securing Generative Artificial Intelligence with Parallel Magnetic Tunnel Junction True Randomness
Advanced Intelligent Systems, EarlyView.True random numbers can protect generative artificial intelligence (GAI) models from attacks. A highly parallel, spin‐transfer torque magnetic tunnel junction‐based system is demonstrated that generates high‐quality, energy‐efficient random numbers.
Youwei Bao, Shuhan Yang, Hyunsoo Yang
wiley +1 more source
An Analytical Gate-All-Around MOSFET Model for Circuit Simulation
Advances in Materials Science and Engineering, 2015 A generic charge-based compact model for undoped (lightly doped) quadruple-gate (QG) and cylindrical-gate MOSFETs using Verilog-A is developed. This model is based on the exact solution of Poisson’s equation with scale length.
Kuan-Chou Lin +2 more
doaj +1 more source
Programmable Logic Devices in Experimental Quantum Optics [PDF]
, 2002 We discuss the unique capabilities of programmable logic devices (PLD's) for experimental quantum optics and describe basic procedures of design and implementation.
Andrews +12 more
core +2 more sources
Advanced Intelligent Systems, EarlyView.A volatile‐switching compact model of electrochemical metallization memory cells for neuromorphic architecture is developed and validated by reliable reproduction of device characterization measurements: I−V sweeps, SET kinetics, relaxation dynamics.
Rana Walied Ahmad +4 more
wiley +1 more source
Architectural design proposal for real time clock for wireless microcontroller unit
EPJ Web of Conferences, 2017 In this project, we are developing an Intellectual properties (IP) which is a dedicated real-time clock (RTC) system for a wireless microcontroller. This IP is developed using Verilog Hardware Description Language (Verilog HDL) and being simulated using ...
Mohd Alias Muhammad Nor Azwan +1 more
doaj +1 more source
A high performance hardware architecture for one bit transform based motion estimation [PDF]
, 2009 Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (IBT) based ME algorithms have low computational complexity.
Akın, Abdulkadir +5 more
core +2 more sources
Bridging HDL Bits and Caffe: An Educational Path to AI Accelerator Design [PDF]
SHS Web of ConferencesAn integrated educational pipeline is presented that bridges hardware description language (HDL) exercises with the Caffe deep learning framework, enabling progression from Verilog fundamentals to the deployment of convolutional neural network ...
Shanker Manjusha +3 more
doaj +1 more source
A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms [PDF]
, 2005 In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard.
Hamzaoglu, Ilker +3 more
core +1 more source