Results 41 to 50 of about 37,772 (288)
Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
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Апаратна реалізація потокового обчислювача логарифму для даних в форматі з фіксованою комою
Mìkrosistemi, Elektronìka ta Akustika, 2020 В роботі розглянуто існуючі підходи до обчислення логарифму. Запропоновано параметризовану апаратну реалізацію потокового обчислювача логарифму за основою 2 для даних в форматі з фіксованою комою, що дозволяє визначати точність обчислень, а також ...
Yaroslav O. Hordiienko +2 more
doaj +1 more source
A High performance and low power hardware architecture for H.264 cavlc algorithm [PDF]
, 2005 In this paper, we present a high performance and low power hard-ware architecture for real-time implementation of Context Adap-tive Variable Length Coding (CAVLC) algorithm used in H.264 / MPEG4 Part 10 video coding standard. This hardware is designed to
Hamzaoğlu, İlker, Şahin, Esra
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An empirical evaluation of High-Level Synthesis languages and tools for database acceleration [PDF]
, 2014 High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms depends on requirements such ...
Arcas Abella, Oriol +9 more
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An Analytical Gate-All-Around MOSFET Model for Circuit Simulation
Advances in Materials Science and Engineering, 2015 A generic charge-based compact model for undoped (lightly doped) quadruple-gate (QG) and cylindrical-gate MOSFETs using Verilog-A is developed. This model is based on the exact solution of Poisson’s equation with scale length.
Kuan-Chou Lin +2 more
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Advanced Intelligent Systems, EarlyView.This study presents the neural network SPICE integration platform (NSIP), a novel simulation framework for FeFET‐based crossbar arrays in neuromorphic computing. NSIP accurately models synaptic behavior, evaluates inference accuracy, and optimizes process variations.
Juhwan Park +3 more
wiley +1 more source
Architectural design proposal for real time clock for wireless microcontroller unit
EPJ Web of Conferences, 2017 In this project, we are developing an Intellectual properties (IP) which is a dedicated real-time clock (RTC) system for a wireless microcontroller. This IP is developed using Verilog Hardware Description Language (Verilog HDL) and being simulated using ...
Mohd Alias Muhammad Nor Azwan +1 more
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International Journal of Circuit Theory and Applications, EarlyView.Method for automated asynchronous adaptation to high dynamic range lighting conditions during image acquisition. ABSTRACT This paper introduces an image formation technique that realizes automatic adaptation to the illumination conditions during image capture.
Yassine Lamouaraa‐Sedlackova +2 more
wiley +1 more source
Description styles of fault-tolerant finite state machines for unmanned aerial vehicles
Радіоелектронні і комп'ютерні системиThe subject matter of this article is finite state machines (FSMs), which are used as control devices in unmanned aerial vehicles (UAVs). The goal of this study is to develop description styles for fault-tolerant FSMs in hardware description languages ...
Valery Salauyou
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An efficient hardware architecture for H.264 adaptive deblocking filter algorithm [PDF]
, 2006 This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard.
Hamzaoglu, Ilker +2 more
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