Results 51 to 60 of about 37,772 (288)

Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS

Electronics, 2020
This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced.
A. Ballo, Michele Bottaro, A. D. Grasso, G. Palumbo   +3 more
semanticscholar   +1 more source

V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

IEEE Open Journal of Circuits and Systems
This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into Verilog-A code, enabling concurrent simulation of analog and ...
Chao Wang, Yicong Shao, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li   +9 more
doaj   +1 more source

A High permormance hardware architecture for an sad reuse based hierarchical motion estimation algorithm for H.264 video coding [PDF]

, 2005
In this paper, we present a high performance and low cost hardware architecture for real-time implementation of an SAD reuse based hierarchical motion estimation algorithm for H.264 / MPEG4 Part 10 video coding.
Ates, Hasan F., Ateş, Hasan F., Hamzaoglu, Ilker, Hamzaoğlu, İlker, Yalcin, Sinan, Yalçın, Sinan   +5 more
core  

Design of Novel Algorithm and Architecture for Gaussian Based Color Image Enhancement System for Real Time Applications

, 2013
This paper presents the development of a new algorithm for Gaussian based color image enhancement system. The algorithm has been designed into architecture suitable for FPGA/ASIC implementation. The color image enhancement is achieved by first convolving
A.K. Jain, D. Jobson, H. Cheng, M. Zhang
core   +1 more source

Verilog HDL and its ancestors and descendants

Proc. ACM Program. Lang., 2020
This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware ...
Peter Flake, P. Moorby, S. Golson, A. Salz, S. Davidmann   +4 more
semanticscholar   +1 more source

A Single‐Stage Differential Amplifier Using Organic Electrochemical Transistors

Advanced Electronic Materials, Volume 11, Issue 9, June 2025.
A three‐transistor differential amplifier using depletion‐mode organic electrochemical transistors is implemented that offers a common‐mode rejection ratio of up to ≈20 dB. Compared to a Wheatstone bridge amplifier, ECG recordings with this amplifier showed improved signal‐to‐noise ratio, gain, and power consumption.
Farnaz Fahimi Hanzaee, Ivan B. Dimov, Luke W. Gatecliff, Richard H. Bayford, George G. Malliaras, Andreas Demosthenous, Nick de N. Donaldson   +6 more
wiley   +1 more source

Behavioral consistency of C and verilog programs using bounded model checking [PDF]

, 2003
Edmund M. Clarke, Daniel Kroening, Karen Yorav   +2 more
  +4 more sources

Hardware/Software Partitioning in Verilog [PDF]

, 2002
نقترح في هذه الورقة نهجًا جبريًا لتقسيم الأجهزة/البرامج في Verilog HDL. نستكشف مجموعة من القوانين الجبرية لبرامج Verilog، والتي نصمم منها مجموعة من القواعد الجبرية القائمة على بناء الجملة لإجراء تقسيم الأجهزة/البرامج. لغة التحديد المشترك ولغات وصف الأجهزة والبرامج المستهدفة هي مجموعات فرعية محددة من Verilog، والتي تحققنا بنجاح من صحة عملية التقسيم عن ...
Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang   +3 more
openaire   +3 more sources

Steep‐Slope IGZO Transistor Monolithically Integrated with Initialization‐Free Ag/Ti/Hf0.8Zr0.2O2 Atomic Threshold Switch

Advanced Electronic Materials, Volume 11, Issue 9, June 2025.
In this study, a steep‐slope In‐Ga‐Zn‐O (IGZO) field‐effect transistor (FET) integrated with an Ag/Ti/Hf0.8Zr0.2O2 atomic threshold switch (ATS) is presented. This device achieves sub‐60 mV dec−1 switching, combining low‐voltage ATS switching with IGZO FETs for low power applications.
Junmo Park, Hanggyo Jung, Deokjoon Eom, Heesoo Lee, Hyunhee Kim, Yonghoon Kim, Jongwook Jeon, Hyoungsub Kim   +7 more
wiley   +1 more source

A Logistic Map Runge Kutta-4 Solution for FPGA Using Fixed Point Representation

Chaos Theory and Applications, 2019
Logistic map can show simple chaotic behavior pattern. Chaotic patterns with their irregularity and unpredictability properties are often used for random number generation and encryption.
Emre Güngör, Enver Cavus, İhsan Pehlivan   +2 more
doaj