Results 61 to 70 of about 24,676 (260)
Advanced Intelligent Systems, Volume 8, Issue 1, January 2026.An amorphous indium–gallium–zinc–oxide (IGZO)‐based optoelectronic neuromorphic system integrating light guides is introduced. The IGZO‐based optoelectronic synaptic transistor demonstrates high retention through a negative gate bias and emulates synaptic plasticity.
Yumin Yun +6 more
wiley +1 more source
New Difference Triangle Sets by a Field‐Programmable Gate Array‐Based Search Technique
Journal of Combinatorial Designs, Volume 34, Issue 1, Page 37-50, January 2026.ABSTRACT We provide some difference triangle sets with scopes that improve upon the best known values. These are found with purpose‐built digital circuits realized with field‐programmable gate arrays (FPGAs) rather than software algorithms running on general‐purpose processors.
Mohannad Shehadeh +2 more
wiley +1 more source
Future InternetWith continuous advancements in semiconductor technology, mastering efficient designs of high-quality and advanced chips has become an important part of science and technology education.
Pin-Chieh Hsieh +5 more
doaj +1 more source
An Extended Amplitude Range Readout Circuit for Charged Particle Detection–BEAR 2
Journal of Geophysical Research: Space Physics, Volume 131, Issue 1, January 2026.Abstract Charge sensitive amplifiers (CSA) form the first stage of most detector readout circuits. The operating range of the readout circuits depends on the saturation limits of the Charge sensitive amplifiers, thereby limiting the range of the detector system as well. A number of methods have been introduced to extend the dynamic range of the readout
A. Antony Gomez +5 more
wiley +1 more source
A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment [PDF]
Radioengineering, 2016 This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a ...
V. R. Gonzalez-Diaz +3 more
doaj
A Strategy Language for Testing Register Transfer Level Logic [PDF]
, 2009 The development of modern ICs requires a huge investment in RTL verification. This is a reflection of brisk release schedules and the complexity of contemporary chip designs.
Katelman, Michael, Meseguer, Jos??
core
Exploring Posit Multiplication: A Comprehensive Review of Booth and Logarithmic Mantissa Methods
IET Computers &Digital Techniques, Volume 2026, Issue 1, 2026.The posit number system represents a significant advancement aimed at replacing the current IEEE floating‐point standard in a seamless manner. With its notable dynamic range and gradually tapering precision, a smaller posit can closely match the performance of a larger floating‐point number in representing decimal values.
Thalla Narasimha Swetha +3 more
wiley +1 more source
Implementation of Loop Pipelining and Assignment Inlining in the C-to-HDL Translator
Труды Института системного программирования РАН, 2018 Implementing algorithms for field-programmable gate arrays using a hardware description language is a complex task. Therefore, it would be useful to have a tool that can efficiently translate an algorithm from a high-level language to a hardware ...
Alexey Merkulov, Andrey Belevantsev
doaj
Advanced Intelligent Systems, Volume 7, Issue 11, November 2025.This study presents the neural network SPICE integration platform (NSIP), a novel simulation framework for FeFET‐based crossbar arrays in neuromorphic computing. NSIP accurately models synaptic behavior, evaluates inference accuracy, and optimizes process variations.
Juhwan Park +3 more
wiley +1 more source
Optimizations in Dynamic Binary Translation
Труды Института системного программирования РАН, 2018 We suggest using OpenCL standard for programming FPGA devices that are used as accelerators in a heterogeneous system. We describe the implementation of a subset of OpenCL that is required for organizing data exchange and task management for FPGAs given ...
Andrey Belevantsev +2 more
doaj