Results 61 to 70 of about 37,772 (288)

Demystifying Regulating Active Rectifiers for Energy Harvesting Systems: A Tutorial Assisted by Verilog-A Models

IEEE Access, 2023
In this paper the design of regulated active rectifiers (RARs) is addressed, with emphasis on energy harvesting applications. After an insightful overview of the main topologies of RARs, the analytical models are discussed and extended.
Andrea Ballo, Alfio Dario Grasso, Marco Privitera   +2 more
doaj   +1 more source

A Physics‐Based Compact Model for Ferroelectric Capacitors Operating Down to Deep Cryogenic Temperatures for Applications in Analog Memory and Neuromorphic Architectures

Advanced Electronic Materials, Volume 11, Issue 9, June 2025.
A compact model for ferroelectric thin‐film capacitors operating under different electric fields and temperatures is reported. The model can reproduce polarization switching down to 4 K, making them suitable for quantum computing and space technologies.
Ella Paasio, Rikhard Ranta, Sayani Majumdar   +2 more
wiley   +1 more source

A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms [PDF]

, 2005
In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard.
Hamzaoglu, Ilker, Hamzaoğlu, İlker, Tasdizen, Ozgur, Taşdizen, Özgür   +3 more
core   +1 more source

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

, 2018
Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors.
Gupta, Aarti, Huang, Bo-Yuan, Malik, Sharad, Subramanyan, Pramod, Vizel, Yakir, Zhang, Hongce   +5 more
core   +1 more source

Machine Learning‐Driven Extraction of Hybrid Compact Models Integrating Neural Networks and Berkeley Short‐Channel Insulated‐Gate Field‐Effect Transistor Model‐Common Multigate for Multidevice Applications

Advanced Intelligent Systems, Volume 7, Issue 5, May 2025.
This research presents a machine learning approach integrating Berkeley short‐channel IGFET model‐common multigate models with an error‐correction neural network to expedite accurate compact model generation for semiconductor devices. Utilizing a hypernetwork, the method eliminates time‐consuming and laborsome parameter tuning and allows simultaneous ...
Seungjoon Eom, Seunghwan Lee, Hyeok Yun, Kyeongrae Cho, Soomin Kim, Rockhyun Baek   +5 more
wiley   +1 more source

High performance hardware architecture for half-pixel accurate H.264 motion estimation [PDF]

, 2006
In this paper, we present a high performance and low cost hardware architecture for real-time implementation of half-pel accurate variable block size motion estimation for H.264 / MPEG4 Part 10 video coding.
Hamzaoğlu, İlker, Yalçın, Sinan
core  

Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add [PDF]

, 2018
The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now ...
Cristal Kestelman, Adrián, Palomar Pérez, Óscar, Ratkovic, Ivan, Stanic, Milan, Unsal, Osman Sabri, Valero Cortés, Mateo   +5 more
core   +2 more sources

Volatile MoS2 Memristors with Lateral Silver Ion Migration for Artificial Neuron Applications

Small Science, Volume 5, Issue 5, May 2025.
This article investigates lateral memristors made from metal‐organic chemical vapor deposition‐grown multilayer molybdenum disulfide, which exhibit repeatable, forming‐free resistive switching with low voltages and fast‐switching times. The switching mechanism based on silver ion surface migration is corroborated through electronic transport modeling ...
Sofía Cruces, Mohit Dineshkumar Ganeriwala, Jimin Lee, Lukas Völkel, Dennis Braun, Annika Grundmann, Ke Ran, Enrique González Marín, Holger Kalisch, Michael Heuken, Andrei Vescan, Joachim Mayer, Andrés Godoy, Alwin Daus, Max Christian Lemme   +14 more
wiley   +1 more source

Generative AI Assertions in UVM-Based System Verilog Functional Verification

Systems
This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal ...
Valentin Radu, Diana Dranga, Catalin Dumitrescu, Alina Iuliana Tabirca, Maria Cristina Stefan   +4 more
doaj   +1 more source

Investigation on Artificial Intelligence Hardware Architecture Design Based on Logic‐in‐Memory Ferroelectric Fin Field‐Effect Transistor at Sub‐3nm Technology Nodes

Advanced Intelligent Systems, Volume 7, Issue 2, February 2025.
This article examines Logic‐in‐Memory (LiM) technology employing Ferroelectric Fin Field‐Effect Transistor for sub‐3 nm nodes, focusing on system‐level implications. LiM circuit performance, including full adder, ternary content‐addressable memory, and flip‐flop, is evaluated using a Verilog‐A model of ferroelectric capacitor.
Changho Ra, Huijun Kim, Juhwan Park, Gwanoh Youn, Uyong Lee, Junsu Heo, Chester Sungchung Park, Jongwook Jeon   +7 more
wiley   +1 more source