Results 71 to 80 of about 37,772 (288)
Implementation of Loop Pipelining and Assignment Inlining in the C-to-HDL Translator
Труды Института системного программирования РАН, 2018 Implementing algorithms for field-programmable gate arrays using a hardware description language is a complex task. Therefore, it would be useful to have a tool that can efficiently translate an algorithm from a high-level language to a hardware ...
Alexey Merkulov, Andrey Belevantsev
doaj
Journal of Engineering, 2023 It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display.
Asma Taha Saadoon
doaj +1 more source
IET Cyber-Physical Systems: Theory &Applications, Volume 10, Issue 1, January/December 2025.A cookie contains a session ID that is a unique number generated by the server. The proposed generator is suitable for all types of web applications, because it requires the smallest area of only 134 Gate Equivalent (GE) on the application specific integrated circuit (ASIC) for its execution.
Kavita Bhatia +3 more
wiley +1 more source
A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment [PDF]
Radioengineering, 2016 This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a ...
V. R. Gonzalez-Diaz +3 more
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BDAQ53, a versatile pixel detector readout and test system for the ATLAS and CMS HL-LHC upgrades
, 2020 BDAQ53 is a readout system and verification framework for hybrid pixel detector readout chips of the RD53 family. These chips are designed for the upgrade of the inner tracking detectors of the ATLAS and CMS experiments.
Daas, Michael +15 more
core +1 more source
Hardware implementation of fast polar decoders based on a simplified control unit
Electronics Letters, Volume 61, Issue 1, January/December 2025.This paper presents the design of a fast simplified successive cancellation decoder based on the proposed simplified controller. Abstract This paper proposes a simplified control unit for fast simplified successive cancellation (FSSC)‐based decoders.
Useok Lee, Myung Hoon Sunwoo
wiley +1 more source
Optimizations in Dynamic Binary Translation
Труды Института системного программирования РАН, 2018 We suggest using OpenCL standard for programming FPGA devices that are used as accelerators in a heterogeneous system. We describe the implementation of a subset of OpenCL that is required for organizing data exchange and task management for FPGAs given ...
Andrey Belevantsev +2 more
doaj
Automatic simulation method for functional equivalence check
Dianzi Jishu Yingyong, 2019 In the mixed-signal chip, behavioral model is widely used to describe the behavior of the analog/mixed-signal blocks in Verilog/Systemverilog/VHDL so as to facilitate the fullchip netlisting for the fullchip Verilog simulation. In order to ensure correct，
Liao Lu +7 more
doaj +1 more source
v2c – A Verilog to C Translator
, 2016 We present v2c, a tool for translating Verilog to C. The tool accepts synthesizable Verilog as input and generates a word-level C program as an output, which we call the software netlist. The generated program is cycle-accurate and bit precise. The translation is based on the synthesis semantics of Verilog.
Rajdeep Mukherjee +2 more
openaire +3 more sources
ASIC Design of a Canonical Huffman Encoder for Computational Storage Drives
Electronics Letters, Volume 61, Issue 1, January/December 2025.The exponential growth of data‐intensive applications, such as cloud computing and artificial intelligence, demands efficient data compression techniques in computational storage drives (CSDs). We propose an advanced application‐specific integrated circuit (ASIC) design for a canonical Huffman encoder, optimised for high throughput and low power ...
Yunxin Huang +3 more
wiley +1 more source