Results 81 to 90 of about 37,772 (288)

VLSI Design of LSTM‐Based ECG Classification for Continuous Cardiac Monitoring on Wearable Devices

Electronics Letters, Volume 61, Issue 1, January/December 2025.
VLSI Design of LSTM‐Based ECG Classification for Continuous Cardiac Monitoring on Wearable Devices. ABSTRACT A portable and efficient electrocardiogram (ECG) classification system is essential for continuous cardiac monitoring in wearable healthcare devices.
Nousheen Akhtar, Jiancun Fan, Abdul Rehman Buzdar, Muaz Ahmed, Ali Raza   +4 more
wiley   +1 more source

Punxa: A Python‐Based RISC‐V System Simulator for Education

Electronics Letters, Volume 61, Issue 1, January/December 2025.
This work introduces an interactive co‐simulation framework that helps students understand computer architecture by bridging hardware and software analysis. Prioritizing detailed analysis over performance, it provides an integrated environment for iterative design, performance evaluation, and debugging.
David Castells‐Rufas, David Novo, Xavier Martorell   +2 more
wiley   +1 more source

A Data-Driven Verilog-A ReRAM Model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models.
I. Messaris, Alexander Serb, S. Stathopoulos, A. Khiat, S. Nikolaidis, T. Prodromakis   +5 more
semanticscholar   +1 more source

ACRIN: Asymmetric Compression‐Recovery Interconnection Network for Inter‐Chip Sparsity Architecture

Electronics Letters, Volume 61, Issue 1, January/December 2025.
We propose an interconnect network architecture designed specifically for a chiplet system targeting sparse large models. The architecture comprises a compression network built with grouped multiplexers (MUXs) and a recovery network based on a BENES network. ABSTRACT Chiplet architecture and sparsity are two pivotal technologies driving the advancement
Jiachen Wang, Yang Wang, Huanyu Wang, Shaojun Wei, Yang Hu, Shouyi Yin   +5 more
wiley   +1 more source

From FPGA to ASIC: A RISC-V processor experience [PDF]

, 2019
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ...
Rojas Morales, Carlos
core   +1 more source

Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback

, 2011
We present the formal verification of a low-power x86 floating-point multiplier. The multiplier operates iteratively and feeds back intermediate results in redundant representation. It supports x87 and SSE instructions in various precisions and can block
Anna Slobodová, Anna Slobodová, Christoph Berg, David Hardin, David M. Russinoff, David M. Russinoff, David M. Russinoff, David M. Russinoff, David M. Russinoff, Dimitri Tan, Erik Reeber, Julien Schmaltz, Mark D Aagaard, Matt Kaufmann, Matt Kaufmann, Peter-Michael Seidel, Roope Kaivola   +16 more
core   +2 more sources

A Bit‐Serial Compute‐Transfer Architecture for High‐Speed Data Processing in Chip‐to‐Chip Systems

Electronics Letters, Volume 61, Issue 1, January/December 2025.
We propose a bit‐serial compute‐transfer architecture for high‐speed data processing in chip‐to‐chip interconnect systems. At the physical layer, bit‐serial computing units are directly connected via the VML interface, integrating data computation and transmission within a single architecture, forming a scalable chip interconnect component.
Xiaoshu Cheng, Siyi Pan, Yiwen Wang, Weiran Ding, Ping Li   +4 more
wiley   +1 more source

Switched Capacitor Voltage Converter [PDF]

, 2019
This project supports IoT development by reducing the power con- sumption and physical footprint of voltage converters. Our switched- capacitor IC design steps down an input of 1:0 - 1:4 V to 0:6 V for a decade of load current from 5 ...
Hsia, Anne, Kidd, Bradford
core   +1 more source

Protection of systems containing IBR from asymmetrical ground faults using zero sequence current with hardware implementation on FPGA

IET Generation, Transmission &Distribution, Volume 19, Issue 1, January/December 2025.
This paper presents a novel method for detection and location of faults on systems containing IBR through the use of zero sequence current. Improvements in detection time are made through the use of Least Error Squared Phasor Estimation. Hardware implementation on an FPGA is used to verify the protection scheme and simulation results.
Jason Pannell, Ramakrishna Gokaraju
wiley   +1 more source

Implementation of SM3 algorithm based on SoPC component

网络与信息安全学报, 2017
Firstly the realization of SM3 on SoC was given.The structure of the algorithm was analyzed mainly,and the algorithm was realized by the Verilog hardware description language,in order to simulate this algorithm,the Altera simulation software ModelSim was
Meng-li SHAO,Yan-mei LI, Xin-chun YIN
doaj   +3 more sources