Results 91 to 100 of about 39,832 (274)

Architectural choices for the Columbia 0.8 Teraflops machine

, 1994
We discuss the hardware design choices made in our 16K-node 0.8 Teraflops supercomputer project, a machine architecture optimized for full QCD calculations.
Airiau, Arsenin, Baker, Higgins, I.V. Arsenin   +4 more
core   +1 more source

CESR-Codificador RS (255,k) eficiente para sistemas reconfigurables

Revista Técnica de la Facultad de Ingeniería
La presente investigación está basada en la obtención de un modelo optimizado para el diseño del Codificador RS-Reed Solomon, orientado a sistemas reconfigurables.
Cecilia Esperanza Sandoval Ruiz, Antonio S Fedón Rovira   +1 more
doaj  

Algorithms for extracting subsystems from a multilevel representation of a system of Boolean functions for joint minimization

Informatika
Objectives. The purpose of experimental research is to determine the effectiveness of new algorithms for extracting the so-called connected subsystems from formula descriptions of the original system of Boolean functions.
P. N. Bibilo, N. A. Kirienko, V. I. Romanov   +2 more
doaj   +1 more source

FPGA realization of four chaotic interference cases in a terrestrial trajectory model and application in image transmission. [PDF]

Sci Rep, 2023
Estudillo-Valdez MA, Adeyemi VA, Tlelo-Cuautle E, Sandoval-Ibarra Y, Nuñez-Perez JC.   +4 more
europepmc   +1 more source

Towards CRYSTALS-Kyber VHDL Implementation

, 2021
Sara Ricci, Petr Jedlička, Peter Cíbik, Petr Dzurenda, Lukáš Malina, Jan Hajný   +5 more
openalex   +1 more source

Automated Test Case Generation for Digital System Designs: A Mapping Study on VHDL, Verilog, and SystemVerilog Description Languages [PDF]

, 2020
Ashish Alape Vivekananda, Eduard Paul Enoiu   +1 more
openalex   +1 more source

VHDL-AMS based genetic optimization of a fuzzy logic controller for automotive active suspension systems

, 2005
This paper presents a new type of fuzzy logic controller (FLC) membership functions for automotive active suspension systems. The shapes of the membership functions are irregular and optimized using a genetic algorithm (GA).
Kazmierski, Tom, Wang, Leran
core  

Bridging high-level synthesis to RTL technology libraries [PDF]

, 1991
The output of high-level synthesis typically consists of a netlist of generic RTL components and a state sequencing table. While module generators and logic synthesis tools can be used to map RTL components into standard cells or layout geometries, they ...
Dutt, Nikil D., Kipps, James R.
core  

Static Analysis of VHDL Source Code: the SAVE Project [PDF]

, 1996
Mirella Mastretti, M. Busi, Roberto Sarvello, Maurizio Sturlesi, Sergio Tomasello   +4 more
openalex   +1 more source

Programación modular de funciones para codificación turbo producto sobre FPGA

Revista Técnica de la Facultad de Ingeniería
En este artículo se realiza una breve revisión de los conceptos de códigos turbo producto, con el propósito de diseñar una alternativa basada en el alto grado de paralelismo disponible en los dispositivos de hardware reconfigurables, como es el caso de ...
Cecilia Esperanza Sandoval Ruiz
doaj