Results 71 to 80 of about 12,898 (231)

Cadê o Kauê? Co‐design and acceptability testing of a chat‐story aimed at enhancing youth participation in the promotion of mental health in Brazil

Journal of Child Psychology and Psychiatry, Volume 66, Issue 5, Page 697-715, May 2025.
Background Adolescent mental health is vital for public health, yet many interventions fail to recognise adolescents as proactive community contributors. This paper discusses the co‐design and acceptability testing of a chat‐story intervention to enhance Brazilian adolescents' participation in the promotion of mental health in their peer communities ...
Gabriela Pavarini, Sheila Giardini Murta, Josimar Antônio de Alcântara Mendes, Felipe Rodrigues Siston, Rafa Ribeiro Alves de Souza, Rafaela de Oliveira da Cunha, Julyana Alves Ferreira, Victor Hugo de Lima de Santos, Brenda Thallys Rocha Seabra, Talk2U, Nicolás Ferrario, Lu Suarez Battan, Bia Matera, Iasmin Coni, Lucca Rosa Pereira, Thayna Iglesias, Ana Luiza Savi, Daniel Foscarini, Kathia Calil, Felipe Corvello, Sômolo Silvestre Salvador, Amparo Guindón, Silvia Lordello, Larissa Polejack, Alice Christovam Constantino, Alicia Mendes, Ana Clara Freitas Ferreira, Ana Vitória Oliveira da Silva, Brenda lorrane Ferreira Feitosa, Alves, Emerson Gomes dos Santos, Hevellyn Sofia Elvino Pinheiro, Iasmyn Brito dos Santos, Isis Santos Goulart, Jamili Maine Lima Campos, Maria Layza Paixão, Milena Sousa, Mutula Manuel Simão João, Natália Samuel Pitcella Borba, Raissa Barbosa da Silva, Raissa Amarante, Yasmin Bilek, Yasmin Flores da Silva, Gabriela Staerke de Rezende, Jonas de Oliveira Bertucci, Claudia Cavalcante de Carvalho Weber, Janete Araújo da Silva, Rodrigo Araújo Magalhães, Rosimeire Aguiar Pereira Lopes, Mikael Silva Rocha, Ana Paula Santiago S. Andrade, Fernanda Bernardes Silveira Costa, Maria Salete Guerra Maranhão Bezerra, Ilina Singh, Gina Vieira Ponte, Thiago Freire, Tony Marcelo Gomes de Oliveira   +56 more
wiley   +1 more source

VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design [PDF]

, 2018
In comparison to conventional CMOS (non-adiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level.
Viv A. Bartlett, Sachin Maheshwari, Kale, I., Izzet Kale, Maheshwari, S., Bartlett, V.   +5 more
core   +1 more source

Large scale system design aided by modelling and DES simulation: A Petri net approach

Software: Practice and Experience, Volume 55, Issue 2, Page 243-271, February 2025.
Abstract The study of real discrete event systems requires the use of models to cope with complexity and large scale. The only way to understand and analyse their behaviour prior to implementation is, in practice, through distributed simulation. Although it is a widely studied discipline, the difficulty of developing efficient distributed simulation ...
Unai Arronategui, José Ángel Bañares, José Manuel Colom   +2 more
wiley   +1 more source

Rapid-prototyping of high-performance RISC cores with VHDL [PDF]

, 1997
In this paper we present some experiences we have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications.
Marrero, G., Nunez, A., Bautista, T., Carballo, P. P.   +3 more
core  

EthVault: A Secure and Resource‐Conscious FPGA‐Based Ethereum Cold Wallet

IET Blockchain, Volume 5, Issue 1, January/December 2025.
This work presents EthVault, the first hardware‐based Ethereum hierarchical deterministic cold wallet, featuring FPGA implementations of key cryptographic algorithms for secure key generation. A novel ECC architecture resilient to side‐channel and timing attacks, along with an efficient child key derivation function, are introduced. Implementation on a
Joel Poncha Lemayian, Ghyslain Gagnon, Kaiwen Zhang, Pascal Giard   +3 more
wiley   +1 more source

Modelling, Simulation and Verification of 4-phase Adiabatic Logic Design: A VHDL-Based Approach [PDF]

, 2019
The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases,
Kale, Izzet, Maheshwari, Sachin, Bartlett, Viv, Kale, I., Maheshwari, S., Bartlett, V.   +5 more
core   +1 more source

Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

Jurnal Rekayasa Elektrika, 2012
A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others.
. Zulfikar
doaj   +1 more source

Independent Task Scheduling in Multi‐Core Systems: A Hardware‐Based Approach for Optimising Energy and Thermal Efficiency

IET Cyber-Physical Systems: Theory &Applications, Volume 10, Issue 1, January/December 2025.
This paper introduces an online distributed hardware scheduler that outperforms similar schedulers in terms of performance, predictability, power and energy consumption and temperature management. Implementing the scheduler in hardware results in fewer clock cycles, lower latency and greater efficiency compared to software implementations.
Mohammadreza Saberikia, Hakem Beitollahi, Hamed Farbeh   +2 more
wiley   +1 more source

PERENCANAAN DAN PEMBUATAN JAM DIGITAL SEBAGAI TIMER ADZAN OTOMATIS MENGGUNAKAN VHDL [PDF]

, 2002
Kebutuhan akan ketepatan dan keakuratan waktu adzan adalah merupakan hal yang sangat penting. Dengan menggunakan Jam Digital sebagai Timer Adzan Otomatis maka ketepatan dan keakuratan waktu adzan akan terpenuhi.
Farid, Safril
core  

Post-Synthesis Back-Annotation of Timing Information in Behavioral VHDL [PDF]

, 1995
This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing constraints of a design which is synthesized by a high-level ...
Behavioral Vhdl Petru, Alexa Doboli, Krzysztof Kuchcinski, Zebo Peng, Petru Eles   +4 more
core