Results 1 to 10 of about 21,924 (247)
Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit
The 1-bit adder circuits are schematized using pass transistor logic (PTL) technique, that’s optimized by the Shannon expansion theorem. The proposed 32 bit carry increment adder (CIA) circuit is designed by bit slice method.
C. Senthilpari +3 more
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Effects of Veratrum nigrum expansion on soil microbial community structure in inner Mongolian mountain steppe [PDF]
BackgroundsThe expansion of poisonous weeds can significantly affect soil microbial communities and their ecosystem functions. In this regard, the poisonous weed Veratrum nigrum has impacted vast regions of Inner Mongolia, with potential impacts on the ...
Bo Pang +7 more
doaj +2 more sources
Analysis of physical expansion and sprawl growth factors of Sari city using Shannon and Heldern entropy models [PDF]
Population growth and rapid urbanization growth in recent decades have not only led to unbalanced physical expansion of cities, but also contributed to growth and development of cities.
Mohammad Mehdi Nasiri Khalili +5 more
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An efficient NPN Boolean matching algorithm based on structural signature and Shannon expansion [PDF]
An efficient pairwise Boolean matching algorithm for solving the problem of matching single-output specified Boolean functions under input negation and/or input permutation and/or output negation (NPN) is proposed in this paper. We present the structural signature (SS) vector, which comprises a first-order signature value, two symmetry marks, and a ...
William N N Hung +2 more
exaly +2 more sources
Logical optimization of Boolean nets using Shannon expansion
A synthesis of logical circuits, comprising functional combination blocks of very large scale integration circuits, is one of the most important tasks of computer-aided design.
P. N. Bibilo, Yu. Y. Lankevich
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GENERALIZATION OF THE SHANNON EXPANSION FOR INCOMPLETELY SPECIFIED FUNCTIONS: THEORY AND APPLICATION
The well known Shannon expansion is not applicable to incompletely specified functions. We propose a theory that merges Boolean and partial algebras and provides creation of new representations and expansions of partially specified functions.
A. A. Prikhozhy
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In the systems of digital VLSI design (Very Large Integrated Circuits), the BDD (Binary Decision Diagram) is used for VLSI verification, as well as for technologically independent optimization as the first stage in the synthesis of logic circuits in ...
P. N. Bibilo, V. I. Romanov
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Logical minimization for combinatorial structure in FPGA
The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA.
P. N. Bibilo +2 more
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Objectives. The problem of circuit implementation of incompletely specified (partial) k-valued logic functions given by tabular representations is considered.
P. N. Bibilo
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A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon Decomposition
In this paper, we describe a new verification method to accelerate the input negation and/or input permutation and/or output negation (NPN) Boolean matching for a single-output completely specified Boolean function.
Juling Zhang +4 more
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