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Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL [PDF]

open access: yesE3S Web of Conferences, 2023
Due to recent developments, the POSIT number system, winch has been planned as a successor for numbers that are expressed in IEEE floating-point, which are in the focus of advances in arithmetic.
Sanivarapu Rambabu   +5 more
doaj   +1 more source

Transfer of Analogies in Traditional Programming Languages to Teaching VHDL

open access: yesSakarya University Journal of Computer and Information Sciences, 2022
One of the languages available to describe a digital system in FPGA is the VHDL language. Since programming in hardware requires a different way of thinking than developing software, the students face some difficulties when trying to design in VHDL ...
Ali Gülbağ, Halit Öztekin
doaj   +1 more source

Implementation and testing of a FSK demodulator

open access: yesRevista Elektrón, 2021
This work describes the implementation and testing of a FSK demodulator, within the framework of a modem re-engineering for navy communications. It was developed over a Spartan 6 XCSLX25 FPGA with its code in VHDL.
Leandro José Ferrari   +3 more
doaj   +1 more source

High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

open access: yesSakarya University Journal of Computer and Information Sciences, 2023
Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures.
Kenan Baysal, Deniz Taşkın
doaj   +1 more source

Synthesis of parallel adders from if-decision diagrams

open access: yesСистемный анализ и прикладная информатика, 2020
Addition is one of the timing critical operations in most of modern processing units. For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation ...
A. A. Prihozhy
doaj   +1 more source

Design and Implementation of Synthesizable VHDL Model for General PCMCIA I/O Cards Controller [PDF]

open access: yesEngineering and Technology Journal, 2008
The portable and nomadic computer market has driven the development ofPCMCIA Cards to address the expansion needs for the user. These cards provide avast variety of hardware devices which are rugged, credit-card sized, lightweight,and power efficient ...
Yousra Abd Mohammed
doaj   +1 more source

Implementing Fuzzy Logic Controller Using VHDL [PDF]

open access: yesEngineering and Technology Journal, 2007
Design of a Fuzzy Logic Controller (FLC) requires more design decisions thanusual, for example rule base, inference engine, defuzzifiction, and data pre- andpost processing.This paper describes a way to implement a simple (FLC) in VHDL, there arethree ...
Yousra A. Mohammed, Leena K. Hashim
doaj   +1 more source

Represent Different Types of Sliding Mode Controllers by VHDL [PDF]

open access: yesEngineering and Technology Journal, 2009
This paper focus on represent and implementation the conventional sliding mode control (SMC), in addition to some types of the common enhancement SMC approaches using reconfigurable hardware technology based on Field Programmable Gate Arrays (FPGAs ...
Yousra Abd Mohammed   +2 more
doaj   +1 more source

Logical minimization for combinatorial structure in FPGA

open access: yesInformatika, 2021
The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA.
P. N. Bibilo   +2 more
doaj   +1 more source

Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL

open access: yesAdvances in Electrical and Electronic Engineering, 2012
This article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency.
Daniel Kekrt   +3 more
doaj   +1 more source

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