Results 31 to 40 of about 35,017 (222)
Image Smoothing Based On FPGA [PDF]
مجلة التربية والعلم, 2013 Programmable logic is emerging as an attractive solution for many digital image processing applications. As image sizes and bit depths grow larger, software has become less useful in the image processing, Field Programmable Gate Array (FPGA) technology ...
Maha A.R. Hasso, Farah Saad Al-Mukhtar
doaj +1 more source
VHDL synthesis system (VSS) : user's manual, version 5.0 [PDF]
, 1992 This report provides instructions for installing and using the VHDL Synthesis System (Version 5.0). VSS is a high level synthesis sytem that synthesizes structures from an abstract description, written with VHDL behavioral constructs.
Chaiyakul, Viraphol +2 more
core
Investigation on the performance of crushed tires as cement replacement in concrete [PDF]
, 2020 The automobile has become an indispensable means of transportation for many households throughout the world. Thus, the disposal of vehicle tires represents a major environmental issue.
Abas, Nor Haslinda +2 more
core
PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems [PDF]
, 2007 We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs).
Fukushige, Toshiyuki +2 more
core +2 more sources
Semantics and synthesis of signals in behavioral VHDL [PDF]
, 1992 Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals.
Gajski, Daniel D. +3 more
core
A mathematical approach towards hardware design [PDF]
, 2010 Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications.
Baaij, Christiaan P.R. +2 more
core +3 more sources
Computer Applications in Engineering Education, Volume 34, Issue 3, May 2026.ABSTRACT The transition from high‐level programming to assembly language constitutes a well‐documented pedagogical bottleneck in computer engineering curricula, particularly in large‐cohort laboratory settings where individualized scaffolding cannot scale.
Federico Garcia Crespi
wiley +1 more source
Structured modeling for VHDL synthesis [PDF]
, 1989 This report will describe a proposed modeling style for the use of the VHSIC Hardware Description Language (VHDL) in design synthesis. We will describe the operations and underlying assumptions of four design models currently understood and used in ...
Gajski, Daniel D., Lis, Joseph S.
core
HMC‐DSR: An FPGA‐Accelerated Clustered Routing Protocol for Scalable and Energy‐Efficient MANETs
Engineering Reports, Volume 8, Issue 4, April 2026.FPGA‐based HMC‐DSR protocol enhances MANET routing with real‐time, energy‐efficient processing, reducing end‐to‐end delay by 20.7%. Power consumption decreased by 15.8%, making it ideal for energy‐constrained systems. Hardware resource optimization achieved a 31.2% reduction in flip‐flops and 27.4% in slice utilization. Throughput improvement of 19.4%,
Arvind Kumar +3 more
wiley +1 more source
Topología Daisy Chain en FPGA para modernización naval: implementación y extensión con ARP
Revista ElektrónLas consolas de operaciones, interfaces de interacción humana implementadas en las Unidades de Superficie del Comando de la Flota Naval, facilitan la visualización de datos críticos y la gestión de sistemas mediante la entrada de comandos por parte de ...
Emiliano Sebastián Gallo +3 more
doaj +1 more source