Results 31 to 40 of about 1,192 (166)
Topología Daisy Chain en FPGA para modernización naval: implementación y extensión con ARP
Revista ElektrónLas consolas de operaciones, interfaces de interacción humana implementadas en las Unidades de Superficie del Comando de la Flota Naval, facilitan la visualización de datos críticos y la gestión de sistemas mediante la entrada de comandos por parte de ...
Emiliano Sebastián Gallo +3 more
doaj +1 more source
A New Strategy to Design Reconfigurable Rivest–Shamir–Adleman (RSA) Accelerators
International Journal of Circuit Theory and Applications, Volume 54, Issue 6, Page 3043-3054, June 2026.A reconfigurable FPGA‐based RSA accelerator is proposed using compression‐based modular multipliers combined with pseudomoduli arithmetic. The approach maps modular exponentiation to low‐cost arithmetic domains and applies a correction stage, achieving significant improvements in delay, operating frequency, and delay–area efficiency compared with ...
Augusto C. B. Vassoler +4 more
wiley +1 more source
Computer Applications in Engineering Education, Volume 34, Issue 3, May 2026.ABSTRACT The transition from high‐level programming to assembly language constitutes a well‐documented pedagogical bottleneck in computer engineering curricula, particularly in large‐cohort laboratory settings where individualized scaffolding cannot scale.
Federico Garcia Crespi
wiley +1 more source
Hardware-Based Sobel Gradient Computations for Sharpness Enhancement
International Journal of Technology, 2019 The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware ...
Daniel Cheok Kiang Kho +2 more
doaj +1 more source
An Embedded Implementation of Discrete Zolotarev Transform Using Hardware-Software Codesign [PDF]
Radioengineering, 2021 The Discrete Zolotarev Transform (DZT) brings an improvement in the field of spectral analysis of non-stationary signals. However, the transformation algorithm called Approximated Discrete Zolotarev Transform (ADZT) suffers from high computational ...
J. Kubak, J. Stastny, P. Sovka
doaj
HMC‐DSR: An FPGA‐Accelerated Clustered Routing Protocol for Scalable and Energy‐Efficient MANETs
Engineering Reports, Volume 8, Issue 4, April 2026.FPGA‐based HMC‐DSR protocol enhances MANET routing with real‐time, energy‐efficient processing, reducing end‐to‐end delay by 20.7%. Power consumption decreased by 15.8%, making it ideal for energy‐constrained systems. Hardware resource optimization achieved a 31.2% reduction in flip‐flops and 27.4% in slice utilization. Throughput improvement of 19.4%,
Arvind Kumar +3 more
wiley +1 more source
Molecular Ecology, Volume 35, Issue 6, March 2026.ABSTRACT The Western honey bee (Apis mellifera) is a globally important pollinator. Its health in natural and managed populations is compromised by numerous factors, including pesticides. Neonicotinoid pesticides are widely used even though they can cause a variety of detrimental effects.
Gursimran Toor +2 more
wiley +1 more source
Signal Processing for the Cluster Wideband Data Burst Mode
Journal of Geophysical Research: Space Physics, Volume 131, Issue 2, February 2026.Abstract The Wideband Data instrument is part of the Cluster spacecraft Wave Experiment Consortium. Its primary data path is a direct connection to the spacecraft data handling system providing real time downlink to the ground stations of the Deep Space Network and Panska Ves Observatory.
K. H. Yearby +2 more
wiley +1 more source
An FSM‐Enabled Reconfigurable Debugging Approach for Area‐Optimized FIR Filters on FPGA Platforms
IET Circuits, Devices &Systems, Volume 2026, Issue 1, 2026.This work introduces a novel method to improve hardware debugging efficiency and decrease computing time by employing a finite state machine (FSM)‐based reconfigurable buffer insertion strategy for optimizing field‐programmable gate array (FPGA) performance.
Murali Anumothu +8 more
wiley +1 more source
IET Power Electronics, Volume 19, Issue 1, January/December 2026.This article presents an analysis of the reconstructed modulators modulation strategy, a technique designed for energy balancing in DC‐to‐AC converters. The study evaluates the performance of this strategy, applied to a seven‐level multilevel cascade inverter. ABSTRACT This paper presents an experimental evaluation of a PWM modulation strategy based on
Yesenia Reyes‐Severiano +5 more
wiley +1 more source