Results 41 to 50 of about 1,192 (166)

Offline Pulse Distribution Strategies for SWISS Rectifier Using Improved PDM at High Switching Frequencies

IET Power Electronics, Volume 19, Issue 1, January/December 2026.
This paper proposes an improved offline pulse density modulation strategy for the SWISS rectifier to achieve low input current distortion and high power factor at high switching frequencies. Experimental results at 38.4 kHz reduce THDi from over 30% to ≈10%, while high‐frequency simulations at 172.8 kHz achieve THDi of 3.3% and PF = 0.9954.
Thuong Ngo‐Phi, Tuyen Nguyen‐Dinh, Nam Nguyen‐Quang, Khuong Nguyen‐Vinh   +3 more
wiley   +1 more source

Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

Jurnal Rekayasa Elektrika, 2015
A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others.
Zulfikar .
doaj   +3 more sources

Design and Performance Analysis of BCH Codes Construction Over Eisenstein Local Rings Zpsω

Journal of Mathematics, Volume 2026, Issue 1, 2026.
A systematic study of BCH codes construction over Eisenstein local rings Zpsω for p ≡ 2(mod3), giving novel structural information to the coding theory, is known as a systematic code study. The rate of code learning, the error‐adjusting program’s potential, and the number of words in the code words are the key factors in determining how well the codes ...
Muhammad Sajjad, Nawaf A. Alqwaifly, Smritijit Sen   +2 more
wiley   +1 more source

Modeling of real bistables in VHDL [PDF]

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference, 2002
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: description of a more complex latch (D-type) and description of a circuit containing three latches where ...
Acosta Jiménez, Antonio José, Barriga Barros, Ángel, Valencia Barrero, Manuel, Bellido Díaz, Manuel Jesús, Huertas Díaz, José Luis   +4 more
openaire   +3 more sources

Bioinspired Fully On‐Chip Learning Implemented on Memristive Neural Networks

Advanced Intelligent Systems, Volume 7, Issue 12, December 2025.
This work proposes a memristive neural network based on van der Waals ferroelectric memristors and contrastive Hebbian learning, enabling fully on‐chip learning. The system achieves over 98% accuracy in pattern recognition with low power consumption (0.321 nJ/image) and high robustness, paving the way for efficient, bioinspired neuromorphic computing ...
Zhixing Wen, Ge Wang, Xiao Luo, Lei Liang, Fan Yang, Xuemei Wang, Qiui Zhang, Jiangang Chen, Qing Liu, Fucai Liu   +9 more
wiley   +1 more source

Algorithms for extracting subsystems from a multilevel representation of a system of Boolean functions for joint minimization

Informatika
Objectives. The purpose of experimental research is to determine the effectiveness of new algorithms for extracting the so-called connected subsystems from formula descriptions of the original system of Boolean functions.
P. N. Bibilo, N. A. Kirienko, V. I. Romanov   +2 more
doaj   +1 more source

VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators. [PDF]

PLoS ONE, 2016
Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications.
Esteban Tlelo-Cuautle, Antonio de Jesus Quintas-Valles, Luis Gerardo de la Fraga, Jose de Jesus Rangel-Magdaleno   +3 more
doaj   +1 more source

Generating Logical Architectures from SysML Behavior Models

Systems Engineering, Volume 28, Issue 6, Page 762-778, November 2025.
ABSTRACT Modeling solution‐neutral operating principles of system features as SysML behavior models enable systems engineers to specify reusable product features for a variety of similar products and to specify and document a product's functionality in an easy‐to‐understand manner.
Christian Granrath, Christopher Kugler, Judith Michael, Bernhard Rumpe, Louis Wachtmeister   +4 more
wiley   +1 more source

CRC 8-bit Encoder-Decoder Component in FPGA using VHDL

Jurnal Elkomika, 2020
AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli.
ANDHI RACHMAN SALEH, SUNNY ARIEF SUDIRO
doaj   +1 more source

Hardware Design for Secure Telemedicine Using A Novel Framework, A New 4D Memristive Chaotic Oscillator, and Dispatched Gray Code Scrambler

Engineering Reports, Volume 7, Issue 10, October 2025.
This work presents a secure telemedicine cryptosystem based on a novel 4D memristive chaotic oscillator and a Dispatched Gray Code Scrambler (DGCS). Implemented on FPGA, the system ensures power‐efficient encryption, making it suitable for real‐time medical image transmission in IoT healthcare environments.
Fritz Nguemo Kemdoum, Serge Raoul Dzonde Naoussi, Gideon Pagnol Ayemtsa Kuete, Justin Roger Mboupda Pone   +3 more
wiley   +1 more source