Results 21 to 30 of about 17,348 (175)
Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language [PDF]
Engineering and Technology Journal, 2010 The wide spread of devices that use image processing in itsfunctions, like cellular phone and digital cameras, increases the need forspecialized processors for these functions as a replacement for softwareprograms that consume more time and resources ...
Waleed Fawwaz Shareef
doaj +1 more source
Informatika, 2023 Objectives. The problem of circuit implementation of incompletely specified (partial) k-valued logic functions given by tabular representations is considered.
P. N. Bibilo
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AmbarishChandurkar/VHDL: VHDL Lab Materials
, 2020 This release contains my VHDL Lab .vhd files made on Xilinx ...
Ambarish Prashant Chandurkar
core +1 more source
FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption [PDF]
Engineering and Technology Journal, 2010 Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs)are highly attractive options for hardware implementations of encryption algorithmsas they provide cryptographic algorithm agility, physical security, and potentiallymuch higher ...
Ashwaq Talib Hashim +2 more
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Supporting Air-Conditioning Controller Design Using Evolutionary Computation
Journal of Advanced Mechanical Design, Systems, and Manufacturing, 2008 In recent years, as part of the remarkable development of electronic techniques, electronic control has been applied to various systems. Many sensors and actuators have been implemented into those systems, and energy efficiency and performance have been ...
Kazuyuki KOJIMA, Keiichi WATANUKI
doaj +1 more source
Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10
Jurnal Elkomika, 2022 ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA +2 more
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FPGA Design and Implementation of Data Covering Based on MD5 Algorithm [PDF]
Engineering and Technology Journal, 2016 The protection of information leads to protection of individual privacy for everyone. This protection is performed using encryption. Many types of encryption may be utilized while the simplest one is the covering of information.
Thamir R. Saeed
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Implementing of Forward Link Channel CDMA2000-1x System by Using Simulink HDL Coder [PDF]
Engineering and Technology Journal, 2012 This work is a proposed simulation for forward link channel of CDMA2000 -1x system by using QPSK, 8QAM and 16QAM, and converting the proposed system to VHDL language by using Simulink HDL Coder for implementing in FPGA board.
Hadi T. Ziboon, Alaa Y. Eisa
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An effective AMS Top-Down Methodology Applied to the Design of a Mixed-SignalUWB System-on-Chip [PDF]
, 2007 The design of Ultra Wideband (UWB) mixed-signal SoC for localization applications in wireless personal area networks is currently investigated by several researchers. The complexity of the design claims for effective top-down methodologies.
Crepaldi, Marco +7 more
core +1 more source
Deadlock Detection in FPGA Design: A Practical Approach
Tsinghua Science and Technology, 2015 Formal verification of VHSIC Hardware Description Language (VHDL) in Field-Programmable Gate Array (FPGA) design has been discussed for many years. In this paper we provide a practical approach to do so.
Dexi Wang +5 more
doaj +1 more source