Results 21 to 30 of about 12,898 (231)
FPGA–implementation of PID-controller by differential evolution optimization
Open Engineering, 2018 We will describe an FPGA implementation of PID-controller that uses differential evolution to optimize the coefficients of the PID controller, which has been implemented in VHDL. The original differential evolution algorithm was improved by ranking based
Hanhila Mika +2 more
doaj +1 more source
An effective AMS Top-Down Methodology Applied to the Design of a Mixed-SignalUWB System-on-Chip [PDF]
, 2007 The design of Ultra Wideband (UWB) mixed-signal SoC for localization applications in wireless personal area networks is currently investigated by several researchers. The complexity of the design claims for effective top-down methodologies.
Crepaldi, Marco +7 more
core +1 more source
Implementing Fuzzy Logic Controller Using VHDL [PDF]
Engineering and Technology Journal, 2007 Design of a Fuzzy Logic Controller (FLC) requires more design decisions thanusual, for example rule base, inference engine, defuzzifiction, and data pre- andpost processing.This paper describes a way to implement a simple (FLC) in VHDL, there arethree ...
Yousra A. Mohammed, Leena K. Hashim
doaj +1 more source
Method for Hardware Acceleration of Convolutional Neural Networks Implemented in FPGA Using VHDL [PDF]
, 2021 Метою кваліфікаційної роботи є розробка методу апаратного прискорення згорткових нейронних мереж на FPGA з використанням VHDL. Проведено аналіз топологій згорткових нейронних мереж; аналіз існуючих алгоритмів навчання згорткових нейронних мереж ...
Шевченко, Д. Ю.
core
Deadlock Detection in FPGA Design: A Practical Approach
Tsinghua Science and Technology, 2015 Formal verification of VHSIC Hardware Description Language (VHDL) in Field-Programmable Gate Array (FPGA) design has been discussed for many years. In this paper we provide a practical approach to do so.
Dexi Wang +5 more
doaj +1 more source
Represent Different Types of Sliding Mode Controllers by VHDL [PDF]
Engineering and Technology Journal, 2009 This paper focus on represent and implementation the conventional sliding mode control (SMC), in addition to some types of the common enhancement SMC approaches using reconfigurable hardware technology based on Field Programmable Gate Arrays (FPGAs ...
Yousra Abd Mohammed +2 more
doaj +1 more source
Logical minimization for combinatorial structure in FPGA
Informatika, 2021 The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA.
P. N. Bibilo +2 more
doaj +1 more source
Hardware-Based Sobel Gradient Computations for Sharpness Enhancement
International Journal of Technology, 2019 The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware ...
Daniel Cheok Kiang Kho +2 more
doaj +1 more source
Reconfigurable SRTM System for Road Traffic in Kingdom of Bahrain
Transport and Telecommunication, 2016 This paper presents reconfigurable hardware architecture for smart road traffic system based on Field Programmable Gate Array (FPGA). The design can be reconfigured for different timing of the traffic signals according to the received and collected data ...
El-Medany Wael +3 more
doaj +1 more source
Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL [PDF]
, 2011 Neurons are complex biological entities which form the basis of nervous systems. Insight can be gained into neuron behavior through the use of computer models and as a result many such models have been developed. However, there exists a trade-off between
Wilson, P.R. +7 more
core +1 more source